VNAND Staircase Gate Contacts With Spacer Isolation
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Solution Overview
Problem
In VNAND flash memory devices, the formation of contact plugs to connect with gate electrodes results in inconsistent heights, leading to potential electrical shorts between adjacent electrodes.
Innovation Solution
A vertical memory device design featuring gate electrodes stacked in a staircase arrangement with spacers and burying patterns to ensure electrical insulation between contact plugs and adjacent gate electrodes, preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to connect with gate electrodes, then electrical connection is achieved, but inconsistent heights cause electrical shorts between adjacent electrodes
Solution Approach 1:
An insulating pattern is introduced as an intermediary element between the contact plug and the adjacent gate electrode. This insulating pattern prevents direct electrical contact between the conductive contact plug and the adjacent gate electrode, thereby eliminating the harmful electrical short while maintaining the intended electrical connection to the target gate electrode.
Solution Approach 2:
The insulating pattern is formed in advance during the manufacturing process, before the contact plug is fully formed or before electrical testing occurs. This preliminary protective measure proactively prevents the potential electrical short from occurring, rather than attempting to correct it after the fact.
2Productivity
If gate electrodes are stacked in staircase arrangement, then vertical integration is achieved, but adjacent electrodes at different heights create short circuit risks
Solution Approach 1:
The insulating pattern serves as a mediator positioned between adjacent gate electrodes at different heights in the staircase arrangement. It provides electrical isolation to the lower portion of adjacent electrodes, enabling the vertical integration to proceed while preventing the harmful effect of shorts between non-planar electrodes.
Solution Approach 2:
The insulating pattern is applied locally at specific positions where adjacent gate electrodes are closest to each other in the staircase arrangement. This localized insulation provides targeted protection precisely where the short circuit risk is highest, without requiring complete insulation of all electrode surfaces.
Data Source
AI summary
A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.