VNAND Word Line Recovery Sequencing by Stack Resistance
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Solution Overview
Problem
Existing semiconductor devices, particularly vertical NAND (VNAND) with high integration, face deterioration issues due to inadequate recovery control methods after read operations.
Innovation Solution
A memory device with a word line area divided into three distinct areas based on resistance values, where recovery operations are sequenced to start at different times based on the resistance values and positions of the stacks, ensuring slower recovery areas are addressed first to prevent over-erasure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform recovery operation is applied to all stacks in vertical NAND memory, then the recovery process is simple to control, but stacks with different resistance values experience inadequate recovery leading to device deterioration
Solution Approach 1:
The memory device divides the word line area into multiple distinct areas (first area, second area, third area) based on resistance values of stacks. Each area is assigned a different recovery sequence, allowing tailored recovery operations for stacks with different electrical characteristics. This segmentation resolves the contradiction by enabling differentiated recovery control that improves reliability without requiring complete redesign of the recovery system.
Solution Approach 2:
The patent applies different recovery sequences to different spatial regions (areas) within the word line area. Stacks in the first area with higher resistance values receive different recovery treatment compared to stacks in the second and third areas with lower resistance values. This local quality approach ensures each region receives appropriate recovery control, improving overall device reliability while maintaining manageable complexity through regional rather than individual stack control.
2Reliability
If recovery operations are performed simultaneously for all areas, then the recovery process is fast and efficient, but stacks with slower recovery speeds experience over-erasure and deterioration
Solution Approach 1:
The patent performs recovery operations in a predetermined sequence based on resistance values, starting with the first area (higher resistance) before moving to the second and third areas (lower resistance). This preliminary action approach ensures that stacks requiring longer recovery time receive their recovery operations first, preventing over-erasure while maintaining overall process efficiency through optimized sequencing rather than simultaneous operations.
Solution Approach 2:
The recovery process is divided into periodic stages corresponding to different areas, with each area receiving recovery operations in sequence. The first area undergoes recovery first, followed by the second area, then the third area. This periodic action structure allows the system to manage recovery speeds efficiently by pacing operations according to the specific recovery requirements of each area, preventing over-erasure while maintaining productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes recovery operations and reduces device deterioration by optimizing the recovery sequence, thereby extending the memory device's lifespan and reliability.
Implementation Method 1
a first area is defined that includes first stacks with a first resistance value in the word line area, a second area is defined that includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value
Data Source
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AI summary
A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.