Wafer-Level Voice Coil Manufacturing via Vertical Plating
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Solution Overview
Problem
Conventional voice coil manufacturing methods face challenges in achieving fine critical dimensions and preventing voids during the plating process, which affects the reliability and efficiency of camera modules, especially in VCM and OIS actuators, due to limitations in coil winding thickness and integration.
Innovation Solution
A method involving the formation of coil patterns on a wafer level package, where a seed metal layer is exposed, followed by selective passivation and photoresist layer formation, allowing for precise plating and filling of via holes with conductive material, and subsequent removal of photoresist layers to achieve thick coil windings with fine critical dimensions and prevent voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional coil winding manufacturing method with RDL type is used, then the manufacturing process is simple, but it is difficult to implement fine critical dimension and the coil thickness is limited
Solution Approach 1:
The patent transitions from planar RDL-type coil winding to three-dimensional vertical coil windings on wafer level package surfaces. This dimensional change enables fine critical dimensions while accommodating thicker coil structures through vertical stacking and multi-layer via connections, resolving the contradiction between precision and complexity.
Solution Approach 2:
The coil structure is divided into multiple segments including seed metal layers, passivation layers, via holes, and photoresist layers. This segmentation allows precise control of each layer's thickness and position, enabling fine critical dimensions while the modular approach manages manufacturing complexity through standardized process steps.
2Reliability
If a passivation layer is formed on a coil pattern, then the coil is protected, but voids are generated during the plating process
Solution Approach 1:
The patent performs preliminary actions by forming via holes through the passivation layer before plating the coil pattern. This sequence prevents void formation by ensuring proper adhesion and material distribution from the outset, while the passivation layer remains in place to protect the coil structure throughout manufacturing.
Solution Approach 2:
The via holes act as intermediaries between the passivation layer and the coil pattern. These structured pathways allow controlled material flow and adhesion during plating, preventing void formation while maintaining the protective function of the passivation layer.
3Volume of stationary object
If the coil thickness is increased to prevent magnetic saturation, then the magnetic flux density is improved, but the manufacturing precision decreases
Solution Approach 1:
The patent achieves increased coil thickness through vertical three-dimensional construction on wafer level packages rather than increasing lateral dimensions. Multiple stacked layers and vertical via connections enable greater effective thickness while maintaining precise lateral dimensional control, resolving the contradiction between volume and precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of voice coils with increased thickness and fine critical dimensions, enhancing the reliability and integration efficiency of camera modules by minimizing voids and maintaining precise electrical connections.
Implementation Method 1
a plating process for the coil pattern is directly performed on the passivation layer
Data Source
AI summary
Provided is a method of manufacturing a voice coil, and more particularly, a method of manufacturing a voice coil in which a coil pattern is formed on a wafer level package. The method includes (a) forming a first coil pattern including a first area in which a first seed metal layer is exposed upward, a second area in which a first passivation layer for forming a via hole in the first area is formed, and a third area in which a first photoresist layer is formed in a portion of the first area and the second area on an upper surface of a wafer, (b) filling an inside of the via hole formed in the first coil pattern with a conductive material and forming first coil windings, and (c) removing the first photoresist layer formed in the third area.