Void Avoidance Verification for Electronic Circuit Design
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Solution Overview
Problem
Existing electronic circuit designs often fail to detect voids and their proximity to nets effectively, leading to performance issues, malfunctioning, or failure, especially in high-performance computing systems, due to the lack of thorough void avoidance verification during the design stage.
Innovation Solution
A system and method for void avoidance verification in electronic circuit designs, utilizing an input engine and a void avoidance engine to identify nets within a threshold distance from voids and generate alerts for double violations, where multiple nets on different sides of the same conductive plane are close to the same void, thereby preventing potential failures before fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional design verification methods are used, then design complexity is reduced, but circuit reliability deteriorates due to undetected void proximity issues
Solution Approach 1:
The patent implements void avoidance verification during the design stage before fabrication, performing preliminary detection of nets within threshold distances from voids. This preliminary action identifies potential reliability issues early, preventing them from manifesting in the final circuit, thus improving reliability without requiring complex post-fabrication testing systems.
Solution Approach 2:
The patent introduces an intermediary verification system that acts as a mediator between the design stage and fabrication stage. This intermediary layer performs automated void avoidance checks, generating reports and alerts about potential issues, thereby improving circuit reliability through systematic verification without directly complicating the fabrication process itself.
2Reliability
If comprehensive void avoidance verification is performed, then circuit reliability is improved, but detection complexity increases
Solution Approach 1:
The verification system performs self-service by automatically accessing the electronic circuit design, identifying voids and nets, calculating distances, and generating verification reports without requiring manual intervention. This automation reduces the difficulty of detection and measurement while comprehensively improving circuit reliability through systematic void avoidance verification.
Solution Approach 2:
The patent replaces manual or mechanical verification methods with an automated computational system that uses algorithms to detect voids, identify nets, calculate distances, and generate reports. This substitution of mechanical/manual processes with automated computational mechanics simplifies the detection process while enabling comprehensive reliability verification.
3Manufacturing precision
If void avoidance verification is implemented, then manufacturing precision is improved, but productivity decreases due to additional verification steps
Solution Approach 1:
By performing void avoidance verification during the design stage as a preliminary action, the system identifies and flags issues before fabrication begins. This early detection prevents costly rework during manufacturing, ultimately improving manufacturing precision while minimizing productivity loss by catching issues before they require physical rework.
Solution Approach 2:
The automated verification system rapidly processes the circuit design to identify void proximity issues, performing the verification check quickly without significantly extending the design cycle. This rushed-through verification approach maintains productivity while ensuring manufacturing precision through comprehensive checking.
Data Source
AI summary
A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.