Void Boundary Structures for Semiconductor Interconnection Capacitance
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Solution Overview
Problem
Semiconductor devices with reduced design rules face challenges in increasing current transmission capability due to increased inner resistance and parasitic capacitance between interconnections, as conventional methods fail to effectively enhance current transmission beyond pre-reduction levels.
Innovation Solution
The implementation of void boundary structures, including a pair of interconnections with plugs and lines of different widths, stacked sequentially, with void boundary layers covering their top surfaces and encompassed by molding or planarization interlayer insulating layers, to define voids between interconnections and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the design rule is reduced to increase integration, then the width and spacing of interconnections are reduced, but the inner resistance increases and current transmission capability deteriorates
Solution Approach 1:
The patent introduces a vertical dimension by forming voids beneath the interconnections (in the lower interlayer insulating layer) to reduce parasitic capacitance. This three-dimensional approach allows the interconnections to maintain smaller cross-sectional areas for high integration while compensating for increased resistance through reduced capacitive loading in the vertical direction.
Solution Approach 2:
The patent changes the physical state of the lower interlayer insulating layer by forming voids (air gaps) within it. This parameter change from solid insulator to void-containing structure reduces the dielectric constant and parasitic capacitance, thereby improving current transmission capability despite reduced interconnection dimensions.
2Productivity
If the design rule is reduced to increase integration, then the spacing between interconnections is reduced, but parasitic capacitance between interconnections increases
Solution Approach 1:
The patent addresses the parasitic capacitance problem by acting in the vertical dimension rather than horizontal. Voids are formed in the lower interlayer insulating layer beneath the interconnections, reducing the capacitance between adjacent interconnections by decreasing the effective dielectric volume between them, thereby allowing closer spacing for higher integration.
Solution Approach 2:
The patent modifies the dielectric parameter of the lower interlayer insulating layer by creating voids within it. This changes the effective dielectric constant in the region between interconnections, reducing parasitic capacitance and enabling closer interconnection spacing for increased integration density.
3Reliability
If voids between interconnections are formed to reduce parasitic capacitance, then current transmission capability improves, but the voids may be unstably formed and filled with insulating layer
Solution Approach 1:
The patent performs preliminary actions to ensure stable void formation: (1) Forms a mandrel pattern in the lower interlayer insulating layer before creating voids, (2) Uses this mandrel as a template for precise void formation, (3) Subsequently forms the upper interlayer insulating layer around the voids to provide mechanical support and prevent collapse. This preliminary structuring ensures void stability throughout the device fabrication and operation.
4Productivity
If the width of interconnections is reduced to increase integration, then the space occupied is reduced, but the inner resistance increases
Solution Approach 1:
The patent compensates for increased resistance due to reduced interconnection width by reducing parasitic capacitance in the vertical dimension. Voids formed in the lower interlayer insulating layer reduce the capacitive load on the interconnections, improving the RC time constant and effective current transmission capability despite smaller cross-sectional areas.
Data Source
AI summary
Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnections. The interconnections may be formed on a semiconductor substrate. An upper width of each of the interconnections may be wider than a lower width thereof. A molding layer encompassing the interconnections may be formed. A void boundary layer covering the molding layer may be formed to define the void between the interconnections.