Void-Free Capping Dielectric Structures for Non-Planar Transistor Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the fabrication of non-planar transistors, existing dielectric deposition processes often result in voids within high aspect ratio recesses, leading to potential contact-to-gate short circuits and affecting the work function of the transistor gate, as well as causing dopant movement or deactivation in the source/drain regions.
Innovation Solution
A high density plasma (HDP) dielectric deposition process is employed to form a substantially void-free capping dielectric structure on non-planar transistor gates, using a process that includes coating the high density plasma chamber walls with the desired dielectric film, introducing reactive gases like oxygen or nitrogen, and controlling the substrate temperature and RF power to achieve a void-free deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing dielectric deposition processes are used to fill high aspect ratio recesses, then the deposition process is simple and fast, but voids form within the recesses leading to contact-to-gate short circuits
Solution Approach 1:
The patent applies parameter changes by modifying deposition conditions including using high density plasma, controlling RF power at 13.56 MHz, maintaining specific pressure ranges (10-100 mTorr), and controlling substrate temperature (200-400°C) to achieve void-free dielectric deposition in high aspect ratio recesses
Solution Approach 2:
The patent replaces conventional thermal CVD or PECVD processes with high density plasma deposition, substituting the traditional heating-based deposition mechanism with a plasma-based mechanism that enables better film conformality and void-free filling of high aspect ratio structures
2Manufacturing precision
If high density plasma deposition is used to achieve void-free capping dielectric structure, then deposition quality improves, but process complexity and time increase
Solution Approach 1:
The patent manages process complexity by optimizing and controlling specific parameters including RF power at 13.56 MHz, pressure between 10-100 mTorr, and substrate temperature at 200-400°C, transforming a complex process into one with well-defined controllable parameters
3Loss of time
If conventional deposition is used, then process time is short, but dopant movement or deactivation occurs in source/drain regions
Solution Approach 1:
The patent resolves the time-quality tradeoff by implementing high density plasma deposition with controlled substrate temperature (200-400°C) and pressure (10-100 mTorr), achieving both rapid deposition and dopant region protection through optimized process parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The HDP process ensures a void-free capping dielectric structure, preventing short circuits and maintaining the integrity of the transistor gate's work function and dopant regions, thereby enhancing the performance and reliability of non-planar transistors.
Implementation Method 1
A high density plasma (HDP) dielectric deposition process is employed to form a substantially void-free capping dielectric structure on non-planar transistor gates
Implementation Method 2
introducing reactive gases like oxygen or nitrogen
Data Source
AI summary
The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process.