Void-Free Semiconductor Contact With Graded Polysilicon Barrier
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to deficiencies, necessitating an improvement in the manufacturing process to address these issues and achieve void-free contacts for enhanced device performance.
Innovation Solution
A semiconductor device with a polysilicon stack comprising undoped and doped layers, surrounded by a dielectric layer, and a void-free contact structure including a barrier and conductive layer, where the barrier layer has varying thicknesses to prevent void formation, is developed. This structure reduces contact resistance and improves device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used in miniaturized semiconductor devices, then device integration is achieved, but void formation occurs in the contact leading to increased contact resistance
Solution Approach 1:
The patent applies preliminary action by forming a graded dopant profile in the polysilicon contact layer before final contact formation. The dopant concentration is gradually increased from the bottom to the top of the polysilicon layer, which preliminarily prepares the contact structure to prevent void formation during subsequent manufacturing steps. This graded profile ensures proper material deposition and prevents vacuum voids from forming during sputtering or CVD processes.
Solution Approach 2:
The patent changes the dopant concentration parameter within the polysilicon contact layer to resolve the contradiction. By creating a graded dopant profile where the dopant concentration varies continuously from the bottom to the top of the layer, the material properties are optimized to prevent void formation while maintaining good electrical contact. This parameter change transforms the uniform structure into a functionally gradient structure that eliminates manufacturing defects.
2Ease of manufacture
If manufacturing complexity is reduced in semiconductor devices, then ease of manufacture improves, but contact resistance increases due to void formation
Solution Approach 1:
The patent changes the dopant concentration parameter within the polysilicon contact layer to resolve the contradiction. By creating a graded dopant profile where the dopant concentration varies continuously from the bottom to the top of the layer, the material properties are optimized to prevent void formation while maintaining good electrical contact. This parameter change transforms the uniform structure into a functionally gradient structure that eliminates manufacturing defects.
Solution Approach 2:
The patent uses composite material structure by combining polysilicon layers with different dopant concentrations in a graded manner. The composite structure consists of multiple regions within the polysilicon contact layer, each with optimized dopant levels for different functions: lower dopant concentration at the bottom for good interface contact and higher dopant concentration at the top for low resistance and void prevention. This composite approach achieves both ease of manufacture and low contact resistance.
Data Source
AI summary
The present disclosure provides a semiconductor device with void-free contacts and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, a dielectric layer disposed over the source/drain structure, and a conductive contact penetrating through the dielectric layer and the source/drain structure, wherein the conductive contact comprises a conductive layer and a barrier layer covering a sidewall and a bottom surface of the conductive layer. A first thickness of the harrier layer on the sidewall of the conductive layer is less than a second thickness of the barrier layer under the bottom surface of the conductive layer.