Void-Free Metal Gate via Wetting Layer Seeding

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Solution Overview

Problem

The formation of voids in metal gate structures due to poor metal gap fill issues during the sputtering process affects the reliability and performance of semiconductor devices, especially when the gate structure is shaped as a trapezoid with a bottom wider than the top.

Innovation Solution

A semiconductor device with a void-free metal gate is achieved by incorporating a wetting layer below the metal layer, which serves as a seeding layer for a selective CVD process, allowing the metal layer to grow without voids, enhancing the metal gap fill property and device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a sputtering process is used to fill the metal layer in the gate structure, then the metal layer can be deposited, but voids are formed due to poor metal gap fill

Engineering Contradiction:
Improvemetal gap fill qualityVSAvoiddevice reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A wetting layer is introduced as an intermediary between the gate structure and the metal layer. This wetting layer improves the adhesion and wetting properties, enabling the metal layer to fill the gate structure completely without forming voids. The wetting layer acts as a mediator that facilitates uniform metal deposition in the trapezoidal gate structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the gate structure is shaped as a trapezoid with bottom wider than top due to etching process limitations, then the etching can be completed, but poor metal gap fill occurs when metal layer is filled

Engineering Contradiction:
Improveetching process feasibilityVSAvoidmetal layer fill quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The wetting layer is formed in advance before the metal layer deposition. This preliminary action prepares the surface with improved wetting properties, ensuring that when the metal layer is subsequently deposited by sputtering, it can uniformly fill the trapezoidal gate structure without voids. The preliminary wetting layer formation addresses the metal fill issue caused by the etching-shaped trapezoid structure.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a metal layer is filled in the exposed trench of the gate structure, then the gate structure is completed, but voids are formed affecting device performance

Engineering Contradiction:
Improvegate structure formation efficiencyVSAvoidvoid-free metal layer
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The wetting layer serves as an intermediary that enables complete and void-free metal layer filling. By improving the surface energy and adhesion properties of the gate structure, the wetting layer ensures that the metal layer can uniformly deposit and fill the entire gate structure during the sputtering process, eliminating voids while maintaining efficient production.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of a wetting layer enables void-free metal growth, improving the reliability and performance of semiconductor devices by ensuring good metal gap fill without voids, thus addressing the limitations of conventional sputtering processes.

Implementation Method 1

A semiconductor device with a void-free metal gate is achieved by incorporating a wetting layer below the metal layer, which serves as a seeding layer for a selective CVD process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS8405143B2Semiconductor device
Publication Date: 2013.03.26 STELLAR SEMICONDUCTOR JAPAN GK
  • US8405143B2 patent drawing
  • US8405143B2 patent drawing
  • US8405143B2 patent drawing

AI summary

A semiconductor device including a substrate, a gate structure, a spacer and source/drain regions is provided. The gate structure is on the substrate, wherein the gate structure includes, from bottom to top, a high-k layer, a work function metal layer, a wetting layer and a metal layer. The spacer is on a sidewall of the gate structure. The source/drain regions are in the substrate beside the gate structure.