Void-Free Polysilicon Floating Gate Formation

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Solution Overview

Problem

In the manufacturing of semiconductor devices, particularly flash memory devices, high aspect ratio openings in semiconductor substrates often result in polysilicon layers with voids, which cannot be removed during planarization, leading to deteriorated electrical characteristics due to oxidation of the floating gate.

Innovation Solution

A method involving the formation of preliminary polysilicon layers with voids, followed by selective etching to expose and remove these voids, allowing subsequent layers to fill the recesses without voids, thereby forming a void-free floating gate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If polysilicon layer is formed to fill high aspect ratio openings, then the opening is filled, but voids are generated in the polysilicon layer

Engineering Contradiction:

Improvefilling of openingVSAvoidvoid formation in polysilicon layer

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The polysilicon layer formation process is segmented into multiple steps: forming a preliminary polysilicon layer, selectively removing it from non-opening regions, and then forming the final polysilicon layer. This segmentation allows voids to be exposed and removed in the preliminary layer, preventing their propagation to the final structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A preliminary polysilicon layer is formed before the final polysilicon layer. This preliminary layer serves as a sacrificial structure that allows voids to be exposed and removed through selective etching, preventing void formation in the final polysilicon layer that will become the floating gate.

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If voids remain in polysilicon layer, then manufacturing is simplified, but electrical characteristics deteriorate due to floating gate oxidation

Engineering Contradiction:

Improvepolysilicon layer formationVSAvoidelectrical characteristics of floating gate

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Voids are selectively extracted from the polysilicon layer structure by forming a preliminary polysilicon layer, selectively removing it from non-opening regions to expose voids, and then removing the voids themselves. This extraction process eliminates the harmful voids while preserving the necessary polysilicon structure for electrical functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The voids that would normally be harmful are converted into a beneficial detection mechanism. By designing the preliminary polysilicon layer removal process, voids are intentionally exposed as a means to detect and remove them, transforming a manufacturing defect into a quality control feature.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Device complexity

If conventional planarization process is used, then manufacturing is simple, but voids cannot be removed

Engineering Contradiction:

Improvemanufacturing processVSAvoidvoid removal capability

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The planarization process is segmented into multiple distinct steps: forming the preliminary polysilicon layer, selectively removing it from non-opening regions, selectively removing voids, and then forming the final polysilicon layer. This segmentation enables void removal capability while maintaining overall process manageability through clear separation of functions.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical characteristics of non-volatile semiconductor memory devices by eliminating voids in the floating gate and improves the manufacturing throughput by ensuring void-free layers in semiconductor substrates.

Implementation Method 1

The first layer is etched in the opening to at least expose the void

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS7629217B2Methods of forming void-free layers in openings of semiconductor substrates

Publication Date: 2009.12.08 SAMSUNG ELECTRONICS CO LTD

AI summary

In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.