Void-Free Dielectric Separation for RRAM Memory Cells
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Solution Overview
Problem
The formation of voids between resistive random-access memory (RRAM) cell structures due to high aspect ratios in inter-cell areas leads to increased risk of dielectric breakdown, reducing the reliability of RRAM arrays by creating leakage paths during high voltage operations.
Innovation Solution
A method involving the deposition of an inter-cell filler layer using a high aspect ratio (HAR) deposition process, followed by recessing to ensure a void-free dielectric structure, which reduces the aspect ratio and prevents void formation in the inter-cell areas, thereby enhancing the reliability of the RRAM array by reducing dielectric breakdown risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional deposition process is used to form dielectric layers in inter-cell areas, then the deposition process is simple and fast, but voids form due to high aspect ratios reducing reliability
Solution Approach 1:
The patent applies preliminary action by performing recessing of the inter-cell area before depositing the dielectric layer. This pre-preparation step creates a modified topology that enables subsequent void-free deposition, solving the reliability issue while maintaining process efficiency.
Solution Approach 2:
The patent segments the dielectric formation process into distinct steps: recessing the inter-cell area, depositing the dielectric layer, and planarizing. This segmentation allows each step to be optimized independently, ensuring void-free formation while managing overall process complexity.
2Reliability
If the inter-cell area is not recessed, then the deposition process is simpler, but voids form creating leakage paths during high voltage operations
Solution Approach 1:
The recessing step is performed as a preliminary action before dielectric deposition, modifying the inter-cell area topology in advance. This prevents void formation during deposition and eliminates leakage paths, improving reliability without significantly complicating the overall manufacturing process.
Solution Approach 2:
The recessing step acts as a preliminary anti-action by removing material to create a geometry that prevents the harmful effect of void formation. By anticipating and counteracting the void formation issue before deposition, the method ensures reliable dielectric structures.
3Manufacturing precision
If high aspect ratio deposition is used to fill inter-cell areas, then void-free structures are achieved, but the deposition process becomes more complex and time-consuming
Solution Approach 1:
By performing recessing as a preliminary action, the patent creates a modified inter-cell area geometry that allows subsequent dielectric deposition to proceed without forming voids. This approach achieves manufacturing precision while maintaining reasonable deposition efficiency, as the difficult HAR deposition is avoided.
Solution Approach 2:
Instead of attempting to deposit dielectric material into high aspect ratio spaces (which causes voids), the patent inverts the approach by first recessing the area to create a favorable geometry for deposition. This reverse engineering of the process sequence achieves void-free formation with standard deposition tools.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents voids in inter-cell areas, reducing the likelihood of dielectric breakdown and leakage paths, thus improving the reliability and manufacturing yield of RRAM arrays by maintaining the integrity of the dielectric structure under high electric field conditions.
Implementation Method 1
depositing an inter-cell filler layer covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.