Void Gate Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor manufacturers strive to decrease feature sizes and increase device density, the proximity of conductive components leads to increased parasitic capacitance, which can decrease device operational speed.
Innovation Solution
The formation of gate spacers with gaps or voids in fin Field-Effect Transistors (finFETs) reduces parasitic capacitance by using low-k dielectric materials and creating openings around the gate stack, thereby reducing the dielectric constant and capacitance between the gate electrode and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased and device density is increased, then device density and operating frequencies are improved, but parasitic capacitance increases which decreases device operational speed
Solution Approach 1:
The gate spacer is configured with a porous structure containing voids or gaps, reducing the effective dielectric constant of the spacer material. This porous configuration decreases parasitic capacitance between the gate electrode and source/drain regions while maintaining the structural integrity needed for high-density device packaging
Solution Approach 2:
The gate spacer employs a composite structure combining different dielectric materials with varying dielectric constants, or combines solid dielectric material with void spaces. This composite approach allows optimization of both capacitance reduction and mechanical support functions in high-density device configurations
2Area of stationary object
If conductive components are placed closer together, then device density is improved, but parasitic capacitance increases which decreases device operational speed
Solution Approach 1:
The porous gate spacer structure with integrated voids reduces the effective dielectric constant in the region between closely-spaced conductive components, thereby decreasing parasitic capacitance while allowing the components to remain in close proximity for high device density
3Strength
If gate spacer is made solid without voids, then structural integrity is improved, but parasitic capacitance increases which decreases device operational speed
Solution Approach 1:
The gate spacer utilizes a porous configuration where voids are strategically positioned to reduce parasitic capacitance while the remaining solid dielectric framework maintains sufficient structural integrity to support the gate electrode and define the spacer geometry
Solution Approach 2:
The gate spacer employs a composite structure combining solid dielectric material with void spaces, where the solid portions provide mechanical strength and the void regions reduce parasitic capacitance, achieving both structural integrity and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing device operational speed and performance, particularly in reduced technology nodes such as 10 nm and below.
Implementation Method 1
The gate spacer is disposed between the gate electrode and the contacts. The gate spacer may reduce parasitic capacitance between the gate electrode and the contacts.
Implementation Method 2
Increases in parasitic capacitance can decrease device operational speed
Data Source
AI summary
Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.