Void-Isolated Control Gates for Dense Vertical Memory Cells
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Solution Overview
Problem
Conventional memory devices face challenges in enhancing storage capacity and performance due to the structural limitations of their memory cells and tiers, which hinder improvements in device efficiency.
Innovation Solution
The introduction of voids and specific dielectric memory elements in the memory device structure allows for a more compact design with reduced coupling capacitance and improved reliability, enabling higher storage density and performance by optimizing the vertical spacing and separation of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in vertically stacked tiers, then storage density is improved, but coupling capacitance between adjacent tiers increases
Solution Approach 1:
The patent extracts the harmful dielectric material between control gates of adjacent tiers and replaces it with voids (empty spaces). This removal eliminates the source of coupling capacitance while preserving the vertical stacking architecture that provides high storage density. The voids are formed by selective removal of dielectric material in regions between control gates, creating isolation zones that prevent electrical coupling.
Solution Approach 2:
The patent introduces a porous or void-containing structure between control gates, where empty spaces (voids) replace solid dielectric material. This porous approach creates electrical isolation between adjacent tiers, reducing coupling capacitance while maintaining the compact vertical arrangement. The voids act as insulating regions that prevent charge leakage and capacitive coupling between stacked memory cells.
2Quantity of substance
If vertical spacing between memory cells is reduced to increase density, then storage capacity is improved, but charge leakage between cells increases
Solution Approach 1:
The patent removes dielectric material to create voids between control gates and memory cells of adjacent tiers. This extraction creates physical separation zones that prevent charge leakage while allowing the memory cells to be vertically stacked with minimal spacing. The voids act as isolation barriers that maintain electrical integrity even when cells are densely packed vertically.
3Area of stationary object
If control gates are positioned closer together to reduce device footprint, then area efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent removes dielectric material to form voids between control gates of adjacent tiers, creating distinct separation zones. This approach allows control gates to be positioned closer together vertically while maintaining manufacturing feasibility. The voids serve as clear boundaries that simplify alignment during fabrication, as the absence of material provides unambiguous reference planes for gate positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a memory device with increased storage density and improved performance by reducing coupling capacitance and preventing charge leakage between memory cells, thereby enhancing the reliability and efficiency of data storage.
Implementation Method 1
a tunnel region including a dielectric material between the channel and the memory element
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.