Void-Lined Source/Drain Contact Isolation for Dense FinFET Layouts
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, achieving adequate electrical isolation between source/drain contacts becomes increasingly challenging, leading to issues with parasitic capacitance and reduced performance in FinFETs.
Innovation Solution
The formation of isolation features with a void between source/drain contacts, utilizing a 'cut last' or 'cut first' process, where a dielectric liner is deposited to create a bowed or reentrant profile shape, significantly reducing the relative permittivity and enhancing electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical isolation between source/drain contacts deteriorates leading to increased parasitic capacitance
Solution Approach 1:
The isolation structure is segmented into multiple layers: a first dielectric layer, a second dielectric layer with different permittivity, and air gaps. This segmentation allows each layer to contribute differently to the overall electrical isolation, with lower permittivity materials positioned strategically to reduce parasitic capacitance between closely spaced source/drain contacts while maintaining physical separation
Solution Approach 2:
Different dielectric materials with specific permittivity values are assigned to different spatial regions between source/drain contacts. The second dielectric layer with lower permittivity is positioned in regions where electric field interaction is most problematic, creating local optimization of electrical isolation properties without compromising overall structure integrity
2Area of stationary object
If source/drain contacts are placed closer together to reduce device area, then integration density increases, but electrical isolation between contacts deteriorates
Solution Approach 1:
The isolation structure uses a composite dielectric system combining multiple materials with different permittivity characteristics. The first dielectric layer provides mechanical support and baseline isolation, while the second dielectric layer with lower permittivity enhances electrical isolation performance, creating a composite structure that achieves both compact dimensions and reliable electrical separation
Solution Approach 2:
Dielectric layers and air gaps serve as intermediary structures between source/drain contacts, mediating the electrical interaction between closely spaced conductive elements. These intermediary layers reduce direct electric field coupling while maintaining physical proximity, enabling compact device layout without sacrificing isolation reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases electrical isolation between source/drain contacts, thereby reducing parasitic capacitance and improving the performance of FinFETs, particularly in high-voltage difference applications like SRAM cells.
Implementation Method 1
a dielectric liner is deposited to create a bowed or reentrant profile shape
Data Source
AI summary
In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.