Void Sealing in Semiconductor Contact Level Dielectric
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Solution Overview
Problem
Conventional techniques for forming stressed dielectric layers in advanced semiconductor devices face challenges with non-uniformities and voids during patterning and metal filling, leading to increased yield losses and reduced transistor performance due to limited conformal deposition capabilities and surface topography.
Innovation Solution
The introduction of a metal confinement liner material to seal or disconnect voids from contact openings before filling with metal-containing material, allowing for more flexible deposition and patterning of interlayer dielectric materials while reducing metal migration and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional techniques are used for forming stressed dielectric layers in advanced semiconductor devices, then deposition and patterning can be performed, but non-uniformities and voids occur during the process leading to contact failures
Solution Approach 1:
A liner material is introduced as an intermediary layer between the metal-containing material and the voids in the interlayer dielectric material. This liner material prevents metal migration into the voids while allowing the stressed dielectric layer to maintain its strain-inducing function. The liner material acts as a barrier that mediates the interaction between the metal filling process and the void structures.
Solution Approach 2:
The liner material is deposited beforehand to prevent the harmful effect of metal migration into voids. By establishing this protective barrier before the metal filling process, the invention preemptively counteracts the potential for contact failures and leakage currents that would otherwise occur during subsequent processing steps.
2Ease of manufacture
If the interlayer dielectric material is deposited to fill contact openings, then contact regions can be formed, but voids between closely spaced transistors connect to contact openings creating leakage paths
Solution Approach 1:
The liner material serves as an intermediary barrier that blocks the connection between voids and contact openings. It is deposited conformally on the inner sidewalls of contact openings, creating a seal that prevents metal-containing material from migrating into voids and eliminating leakage current paths while maintaining the ease of contact opening formation.
Solution Approach 2:
The liner material is applied as a thin film coating on the inner sidewalls of contact openings. This thin film structure provides effective sealing against metal migration while maintaining the overall geometry and fillability of contact openings, enabling easy manufacturing without compromising reliability.
3Reliability
If stress-inducing mechanisms are applied to extremely scaled devices, then transistor performance can be enhanced, but deposition non-uniformities and voids increase due to limited conformal deposition capabilities
Solution Approach 1:
The liner material acts as a mediator that allows the stressed dielectric layer to be deposited with relaxed constraints. By providing this protective barrier first, the system can accommodate the non-uniformities inherent in conformal deposition processes while still achieving the desired stress-inducing effect on transistor channels, thus maintaining transistor performance despite deposition limitations.
Solution Approach 2:
The liner material provides a cushioning effect by being deposited beforehand to compensate for potential deposition non-uniformities. This preliminary layer ensures that even if subsequent stressed dielectric layer deposition is non-uniform, the underlying liner material prevents catastrophic failures and maintains sufficient stress transfer to the transistor channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the probability of contact failures and leakage currents, enabling the application of stress-inducing mechanisms to extremely scaled devices without compromising yield, thus enhancing transistor performance and extending strain-inducing mechanisms to future device generations.
Implementation Method 1
forming a metal confinement liner material on at least a portion of inner sidewalls of the contact opening to suppress metal migration from the contact opening into the void
Implementation Method 2
the interlayer dielectric material comprises a stressed dielectric material for inducing a strain in the semiconductor region
Data Source
AI summary
In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.