Air Gap Inner Spacers in GAA Devices for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in reducing parasitic capacitance between source/drain epitaxial features and high-k metal gates, which affects device performance and manufacturing complexity as ICs scale down.
Innovation Solution
The method involves forming inner spacers with voids between source/drain epitaxial features and high-k metal gates, using a process that includes etching semiconductor layers to create gaps, depositing a dielectric layer that partially fills these gaps, and performing an etch-back process to maintain voids, thereby reducing parasitic capacitance and protecting the source/drain features during channel release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down to improve production efficiency and lower costs, then device dimensions are reduced, but parasitic capacitance of gate electrodes and source/drain features increases
Solution Approach 1:
The patent extracts the harmful dielectric material from the gap between source/drain features and gate electrodes by forming voids (air gaps) in this region. This removal of the high-k dielectric material directly reduces the parasitic capacitance between these components while maintaining the scaled-down device dimensions for improved productivity.
Solution Approach 2:
The patent introduces a porous or void-containing structure in the gap region between source/drain features and gate electrodes. By creating air gaps (effectively porous spaces filled with air instead of dielectric material), the parasitic capacitance is reduced since air has a much lower dielectric constant than the original dielectric material.
2Reliability
If multigate devices are used to improve gate control and reduce OFF-state current, then gate-channel coupling increases, but device complexity increases
Solution Approach 1:
The patent introduces inner spacers as intermediary structures between the source/drain features and the gate electrodes. These spacers act as mediators that provide precise spatial separation and positioning, enabling the complex gate-all-around structure to be manufactured with controlled precision without requiring overly complex fabrication processes.
Solution Approach 2:
The inner spacers are formed in advance before the gate electrodes are deposited. This preliminary action establishes the correct spatial relationships and gaps between components beforehand, simplifying subsequent fabrication steps and reducing the overall device complexity despite the advanced gate control architecture.
3Object-generated harmful factors
If inner spacers with voids are formed to reduce parasitic capacitance, then parasitic capacitance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The inner spacers are formed within the existing semiconductor structure, nesting the spacer formation process within the broader device fabrication sequence. This nested approach allows the voids to be created using standard fabrication techniques applied to already-defined structures, reducing the need for additional high-precision manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing device operating speed and integrating seamlessly with existing semiconductor manufacturing processes while protecting source/drain features during etching.
Implementation Method 1
depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers, wherein the dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers
Data Source
AI summary
A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.