3D Volatile Memory Stack With Bonded Control Logic Layout
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices due to processing conditions and the complexity of control logic devices, which limit memory density and increase power consumption.
Innovation Solution
The method involves forming a microelectronic device by separately creating a first microelectronic device structure with vertical stacks of memory cells and a second microelectronic device structure with control logic devices, then attaching them using oxide bonding, and replacing sacrificial structures with conductive material to facilitate electrical connections and reduce RC values for faster data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are integrated within the base control logic structure underlying the memory array, then electrical communication with memory cells is achieved, but processing conditions limit the configurations and performance of control logic devices
Solution Approach 1:
The patent divides the microelectronic device into two separate structures: a first microelectronic device structure containing the memory array, and a second microelectronic device structure containing the control logic devices. These structures are formed independently and then attached together, allowing each to be optimized separately without being constrained by common processing conditions.
2Adaptability or versatility
If quantities and dimensions of control logic devices are increased to handle complex memory arrays, then control functionality is improved, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where control logic devices are placed within the planar footprint of the memory array to a three-dimensional configuration where control logic devices are stacked vertically above the memory array in a separate structure, effectively utilizing the vertical dimension to reduce the horizontal footprint.
3Adaptability or versatility
If control logic devices are made more complex to handle increased memory array density, then control capability is improved, but real estate consumption increases reducing memory density
Solution Approach 1:
The patent separates the memory array and control logic devices into different structures, allowing the memory array to occupy its optimal space without being encroached upon by control logic devices. This segmentation enables maximum memory density while maintaining full control capability.
Solution Approach 2:
By placing control logic devices in a vertical stack above the memory array rather than alongside it, the patent preserves the horizontal real estate for memory cells while accommodating complex control logic in the vertical dimension.
4Productivity
If traditional fabrication methods are used to form memory array over base control logic structure, then integration is achieved, but reductions in size and improvements in performance are impeded
Solution Approach 1:
The patent divides the fabrication process into separate stages for forming the memory array structure and the control logic structure, each optimized for its specific function. This segmentation simplifies the overall fabrication complexity by allowing independent optimization of each structure's formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of more compact, high-performance memory devices with improved data transfer rates and reduced power consumption by allowing for independent fabrication and attachment of memory and control logic components, addressing the limitations of traditional fabrication methods.
Implementation Method 1
attaching them using oxide bonding
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.