3D Volatile Memory Layout With Over-Staircase CMOS Drivers
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the size and complexity of memory devices, as processing conditions and control logic structures hinder reductions in size and performance improvements.
Innovation Solution
A microelectronic device structure is formed with a first microelectronic device structure comprising global digit lines, multiplexer regions, and vertical stacks of memory cells, where control logic devices are integrated separately in a second microelectronic device structure, reducing the distance between contact structures and high-performance CMOS circuitry for faster operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are integrated within the base control logic structure underlying the memory array, then the device can be manufactured using standard processing conditions, but the device complexity and real estate consumption increase, reducing memory density
Solution Approach 1:
The patent divides the microelectronic device into two separate structures: a first microelectronic device structure containing the memory array, and a second microelectronic device structure containing the control logic devices. This segmentation allows each structure to be optimized independently - the memory array can be manufactured under standard processing conditions while the control logic can be designed with reduced complexity and real estate consumption.
Solution Approach 2:
The control logic devices are extracted from the base control logic structure and placed in a separate second microelectronic device structure. This extraction reduces the complexity and real estate requirements within the memory array structure, allowing for higher memory density while the control logic can be optimized independently for performance.
2Device complexity
If control logic devices are integrated within the base control logic structure, then the device structure is simplified, but the real estate consumption increases and memory density decreases
Solution Approach 1:
By segmenting the device into separate first and second microelectronic device structures, the patent reduces the real estate consumption within the memory array. The control logic devices are placed in the second structure, freeing up space in the first structure for higher memory density, while the overall device remains integrated through electrical connections.
3Device complexity
If the distance between contact structures and high-performance CMOS circuitry is increased, then the device structure is simplified, but the operating speed decreases
Solution Approach 1:
The patent utilizes vertical stacking to reduce the horizontal distance between contact structures and CMOS circuitry. By placing elements in different vertical layers (first microelectronic device structure below second microelectronic device structure), the patent achieves shorter signal paths and faster operations while maintaining structural organization and simplicity.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.