Volatile Memory Bit Line Layout Without Dummy Mats
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Solution Overview
Problem
Volatile memory devices with open bit line structures face challenges in reducing area and increasing cell density due to unnecessary mats at the edge portions, which occupy valuable space and hinder efficient use of chip area.
Innovation Solution
The proposed solution involves a two-stack structure comprising a first normal mat and a first reference mat, connected to sense amplifiers through metal lines, eliminating the need for dummy mats and allowing for a more compact design with increased cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an open bit line structure is used in a volatile memory device, then the device can be simplified in design, but unnecessary mats appear at edge portions causing increased area consumption
Solution Approach 1:
The invention extracts and eliminates the unnecessary dummy mat from the open bit line structure by reconfiguring the bit line connections. Instead of having isolated bit lines at edge portions that require dummy mats, the patent connects these bit lines to sense amplifiers through metal lines, removing the harmful dummy mat structures while preserving the simplified open bit line architecture.
Solution Approach 2:
The invention transitions from a two-dimensional planar layout to a three-dimensional stacked structure by placing reference mats above normal mats in vertical stacking. This dimensional change allows bit lines to be connected across different layers through metal lines, eliminating the need for dummy mats at edge portions while maintaining area efficiency.
2Device complexity
If traditional open bit line structure is used, then design is simpler, but cell density is reduced due to unnecessary mats occupying valuable space
Solution Approach 1:
The invention removes the unnecessary dummy mats from the traditional open bit line structure, freeing up valuable chip area that can then be utilized for additional memory cells. This extraction of harmful elements directly increases cell density while preserving the design simplicity of the open bit line approach.
Solution Approach 2:
The invention merges normal mats and reference mats into a unified two-stack structure where both mat types share common bit line infrastructure. This consolidation eliminates redundant structures and maximizes the number of functional memory cells that can be packed into the available area.
3Reliability
If dummy mats are included in open bit line structure, then edge portions are covered, but area is wasted and cell density decreases
Solution Approach 1:
The invention extracts and eliminates the dummy mat structures from edge portions by implementing alternative bit line connections using metal lines that extend from normal mats to sense amplifiers. This removal of dummy mats recovers wasted area while maintaining proper edge portion coverage through the redesigned connection architecture.
Solution Approach 2:
The invention introduces metal lines as intermediary connection elements that bridge the gap between normal mats and sense amplifiers at edge portions. These metal lines serve as mediators that provide the necessary electrical connections previously achieved through dummy mats, but without the area penalty.
Data Source
AI summary
A memory such as a volatile memory device capable of having a reduced area is provided. The volatile memory device comprises a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier, a first normal mat disposed between the first sense amplifier and the second sense amplifier, and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, and a first reference mat disposed on the first normal mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier and a second complementary bit line connected to the second sense amplifier.