Volatile Memory Error Correction with Adaptive Parity Levels
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Solution Overview
Problem
As the degree of integration of semiconductor chips in memory systems increases, error rates in volatile memory devices are rising, necessitating an efficient error correction technique that maintains performance.
Innovation Solution
A memory system with a memory controller that employs a Compute eXpress Link (CXL) communication protocol, utilizing an error correction level manager and ECC engine to generate parity symbols based on cell reliability and data integrity, enabling efficient error correction through Reed-Solomon codes, with adjustable parity symbol generation for enhanced error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of semiconductor chips is increased, then the memory capacity and performance are improved, but the error rate in volatile memory devices increases
Solution Approach 1:
The patent applies preliminary action by generating parity symbols and performing error correction encoding before data is written to the volatile memory devices. The memory controller proactively creates redundancy information (first and second parity symbols) that will be used later to correct errors, rather than waiting for errors to occur. This advance preparation enables the system to handle higher integration densities while maintaining reliability through pre-computed error correction capabilities.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the error correction level based on data reliability requirements. The system can switch between different correction modes: standard correction using first parity symbols, enhanced correction using both first and second parity symbols, and maximum correction using triple redundancy. This parameter adjustment allows the memory system to adapt its error correction strength to match the integration density and application requirements, resolving the contradiction between capacity and reliability.
2Reliability
If advanced error correction techniques are applied to correct errors in high-density memory, then reliability is improved, but decoding time and processing overhead increase
Solution Approach 1:
The patent applies partial action by implementing tiered error correction strategies. Not all data requires the same level of correction - the system can apply standard correction (first parity symbols only) for most data, and only apply enhanced correction (both first and second parity symbols) when higher reliability is needed. This selective approach reduces the average decoding time while maintaining reliability for critical data, resolving the contradiction between correction capability and processing time.
Solution Approach 2:
The patent segments the error correction process into multiple independent components: first parity symbols for standard correction, second parity symbols for enhanced correction, and triple redundancy for maximum correction. This segmentation allows the memory controller to apply only the necessary correction level for each data access, avoiding the need to always perform the most time-consuming correction operations. The segmented approach enables parallel processing and reduces average decoding time while maintaining high reliability when needed.
Data Source
AI summary
A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller causes different amounts of error correction parity information to be generated depending on a request from a host device and depending on failed memory cell counts. The memory controller includes an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level. The correction levels are based on cell reliability information and data reliability request information. The data reliability request information is associated with the cache line data. An ECC engine generates first parity symbols associated with the cache line data, and may, depending on the ECC control signal, generate additional parity symbols.