Volatile Memory Power Partitioning for Storage Power-Loss Protection

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Solution Overview

Problem

Volatile semiconductor memory devices lose data when power is suddenly cut off, leading to potential data loss in storage devices that utilize both volatile and non-volatile memory components.

Innovation Solution

A storage device with a power loss protection circuit that manages power supply using internal and external spare power sources to maintain power to critical data areas, ensuring data redundancy and protection during power outages by dividing volatile memory into areas receiving duplicate or spare power from multiple sources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile memory is used as buffer memory to temporarily store data, then read and write speeds are improved, but data loss occurs when power is suddenly cut off

Engineering Contradiction:
Improveread and write speedsVSAvoiddata retention during power failure
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The volatile memory is divided into multiple power supply areas, with critical data stored in areas receiving spare power while non-critical data is stored in areas without spare power. This segmentation allows the system to maintain high speed performance while protecting only the most important data from power loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different power supply strategies are applied to different regions of the volatile memory based on data importance. Critical data areas receive dedicated spare power supply, while non-critical areas use standard power supply, optimizing both data protection and power consumption.

Inventive Principle:
Principle #3Local quality

2Reliability

If spare power sources are used to maintain power to critical data areas, then data protection is improved, but device complexity increases

Engineering Contradiction:
Improvedata protection during power failureVSAvoidpower management system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Spare power sources are charged during normal operation when main power is available, preparing energy reserves in advance. When power failure occurs, these pre-charged sources immediately activate to protect critical data without requiring complex real-time power management decisions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A power loss protection circuit acts as an intermediary between the main power source and the volatile memory, automatically managing power distribution and switching to spare power sources when needed, thereby simplifying the overall control architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If all volatile memory areas receive spare power, then data loss is completely prevented, but power consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of providing spare power to all volatile memory areas, the system applies spare power only to the extent necessary for protecting critical data. This partial action approach prevents complete data loss while avoiding the excessive power consumption that would result from protecting all data equally.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP4286981B1Storage device preventing loss of data in situation of lacking power and operating method thereof
Publication Date: 2026.04.01 SAMSUNG ELECTRONICS CO LTD
  • EP4286981B1 patent drawingFigure 1
  • EP4286981B1 patent drawingFigure 2
  • EP4286981B1 patent drawingFigure 3

AI summary

Disclosed is a storage device (1100) including a non-volatile memory (1120) that inputs or outputs data at a request of a host system (110, 210), a volatile memory (1130, 2130) that temporarily stores data input to or output from the non-volatile memory (1120, 2120), an internal spare power source (1150, 2150) that supplies power to a part of the volatile memory (1130) in response to main power supplied from the host system (110, 210) dropping to a first amount or less, and a storage controller (1110, 2110) that controls the non-volatile memory (1120, 2120) and the volatile memory (1130, 2130). The storage controller (1110, 2110) is configured to divide the volatile memory (1130, 2130) into area-received-duplication-power (1131, 2131), and at least one area-received-spare-power (1132, 2132; 1133, 2133), in response to the main power dropping to the first amount or less, to redundantly supply spare power to the area-received-duplication-power (1131, 2131) from an external spare power source (1200; 1400, 2400) and the internal spare power source (1150, 2150) , and to supply the spare power to the at least one area-received-spare-power (1132, 2132; 1133, 2133) from the external spare power source (1200; 1400, 2400).