Volatile Memory Erasure via Refresh Circuitry Control
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Solution Overview
Problem
Current software-based methods for erasing data from DRAM in cloud virtualization are slow and inefficient, leading to potential data privacy breaches and prolonged VM boot times due to the need for sequential memory-write operations, which are not acceptable in cloud computing contexts where quick resource allocation is critical.
Innovation Solution
Implementing a hardware-managed refresh circuitry that prevents refresh operations in volatile memory, allowing charge to leak and effectively zeroing out memory cells, thereby enabling fast and secure data erasure without the need for writing or reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based zeroing operations are used to erase DRAM content, then data privacy is protected, but the erasure time becomes excessively long (minutes for large memory sizes)
Solution Approach 1:
The patent replaces the software-based mechanical writing operation with a hardware-based electrical refresh control mechanism. By controlling the DRAM refresh circuitry to stop refreshing specific memory banks, the data naturally decays to zero state through capacitor discharge, eliminating the need for sequential software write operations. This substitution reduces erasure time from minutes to milliseconds while maintaining data privacy protection.
2Reliability
If software zeroing operations are performed at VM boot time or termination, then memory is sanitized for next user, but the computation overhead and boot time are enormously prolonged
Solution Approach 1:
The patent implements preliminary action by pre-configuring the refresh control circuitry to能够快速 respond to VM termination events. When a VM terminates, the system immediately controls the refresh circuitry to stop refreshing the allocated memory banks, causing data decay. This preliminary setup allows the memory to be sanitized in milliseconds rather than requiring time-consuming software operations, thereby maintaining high VM provisioning speed while ensuring memory sanitization.
3Reliability
If sequential memory-write operations are used to zero out DRAM, then all memory locations are overwritten, but the operation is considerably slow and expensive for large memory sizes
Solution Approach 1:
The patent substitutes the high-power sequential write operations with a low-power refresh control mechanism. By controlling the refresh circuitry to stop refreshing specific banks, the data naturally decays through capacitor discharge without requiring active writing. This approach achieves complete memory coverage while reducing computation cost and power consumption, as the refresh control operates at the hardware level with minimal energy expenditure compared to software-based sequential writes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces data erasure time to milliseconds, ensuring quick resource reallocation and enhanced data privacy by preventing data leakage between users, thus addressing the inefficiencies and security concerns of existing software-based solutions.
Implementation Method 1
Basic DRAM cell 3 consists of one nMOS transistor and one capacitor (FIG. 3). The transistor is used to control access to the storage element (capacitor). The memory state is stored as charge on the capacitor. Since the charge on the capacitor can leak away hence, the need for refreshing when DRAM is used.
Implementation Method 2
Implementing a hardware-managed refresh circuitry that prevents refresh operations in volatile memory, allowing charge to leak and effectively zeroing out memory cells
Data Source
AI summary
A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.