Volatile Memory Runtime Error Repair Control
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Solution Overview
Problem
Volatile memory devices, such as DRAM, face increased bit errors and reduced yield due to shrinking fabrication design rules, leading to operational failures after being mounted in SSDs, as existing repair schemes are ineffective in detecting and addressing errors during normal operation.
Innovation Solution
A method is introduced to control the repair of volatile memory devices by setting a test operation condition with increased error probability, detecting error position information, and performing runtime repairs based on accumulated error information, enhancing the reliability and lifetime of the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional repair schemes are used for DRAM devices, then manufacturing yield can be improved through fault repair during fabrication, but errors occurring after mounting cannot be detected or corrected, leading to operational failures
Solution Approach 1:
The patent applies preliminary action by performing runtime repair operations during the operational phase of the DRAM device. The system proactively detects errors and executes repair schemes while the device is in use, rather than relying solely on post-fabrication repair. This enables the system to address faults before they cause operational failures, thereby improving reliability without requiring complex external intervention systems.
Solution Approach 2:
The DRAM device performs self-diagnosis and self-repair through integrated error detection and correction mechanisms. The system uses internal resources such as spare rows and columns within the memory array to automatically repair faulty cells without requiring external repair equipment or complex control systems from the host computer. This self-service capability improves reliability while keeping the device complexity manageable.
2Measurement precision
If test operation conditions with increased error probability are applied, then error detection capability is improved, but normal operation performance may be affected
Solution Approach 1:
The patent segments the memory array into test object regions and normal operation regions. By dividing the memory space, the system can apply stringent test operation conditions with increased error probability to specific segments for enhanced error detection, while maintaining normal operation conditions in other segments to preserve performance. This segmentation allows the system to improve measurement precision without sacrificing overall productivity.
Solution Approach 2:
The system implements periodic test operations interspersed with normal operations. Rather than continuously applying test conditions that would degrade performance, the system periodically switches between test modes and normal modes. This periodic action allows error detection precision to be improved during test intervals while maintaining high productivity during normal operation intervals, effectively balancing the two requirements.
Data Source
AI summary
A test operation condition of a volatile memory device is set such that an error probability is increased based on the test operation condition, compared to a normal operation condition for a normal operation of the volatile memory device. A test mode is set with respect to a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operation condition during the test mode to detect error position information of errors in data stored in the test object region. A runtime repair operation is performed with respect to the volatile memory device based on the error position information.