Volatile Memory Resume Controller for Low-Power Wake-Up Latency
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Solution Overview
Problem
Conventional processing systems exhibit long wake-up latency when exiting sleep states due to the slow access of BIOS code from non-volatile memory during reinitialization, which is similar to a cold boot process.
Innovation Solution
The system stores resume boot configuration information in volatile memory and maintains power to it during low-power states, allowing the resume controller to access configuration information from non-volatile memory and restore the memory controller, enabling processor cores to complete the boot process efficiently using volatile memory, thereby reducing wake-up latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIOS code is accessed from non-volatile memory during reinitialization, then the processor device can be reinitialized upon exiting sleep state, but the wake-up latency becomes relatively long
Solution Approach 1:
The system performs preliminary action by maintaining volatile memory in a powered state during sleep mode, keeping boot code and configuration information readily accessible. This allows the processor to resume execution quickly without needing to access slower non-volatile memory during wake-up, thus reducing wake-up latency while maintaining reinitialization capability
Solution Approach 2:
The patent introduces volatile memory as an intermediary between non-volatile memory and the processor. During sleep state, volatile memory retains boot code and configuration data, acting as a buffer that enables fast access during wake-up while non-volatile memory provides persistent storage. This intermediary layer resolves the contradiction by providing both fast access (reducing latency) and reliable storage (maintaining reinitialization capability)
2Loss of time
If volatile memory is maintained powered during low-power state, then wake-up latency is reduced, but power consumption increases
Solution Approach 1:
The system applies local quality by selectively maintaining power to only the volatile memory portion that stores boot code and configuration information, rather than keeping the entire processor system powered. This localized power maintenance enables fast wake-up while minimizing overall power consumption during sleep state
Solution Approach 2:
The patent implements partial action by maintaining power to volatile memory at a reduced level during sleep state, sufficient to retain data but consuming less energy than full operation. This partial power maintenance strikes a balance between reducing wake-up latency and minimizing power consumption, avoiding the extremes of complete power cutoff or full power maintenance
Data Source
AI summary
Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.