Volatile Memory Retention Voltage Management
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Solution Overview
Problem
In computer systems with volatile memory, reducing power consumption while maintaining data integrity is challenging due to variations in minimum retention voltage levels among data storage cells, leading to inefficient power usage when protecting defective cells with higher retention voltage levels.
Innovation Solution
A voltage control circuit manages different retention voltage levels for sub-arrays based on test information, providing a lower voltage to sub-arrays without defective cells and a higher voltage to those with defective cells, thereby optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a higher retention voltage level is applied to all sub-arrays to protect defective cells, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies different retention voltage levels to different sub-arrays based on their individual defect characteristics. Sub-arrays with defective cells receive a higher retention voltage level to ensure data integrity, while sub-arrays without defective cells receive a lower retention voltage level to reduce power consumption. This localized differentiation resolves the contradiction by providing high reliability only where necessary.
Solution Approach 2:
The memory array is divided into multiple sub-arrays, each with its own retention voltage control. The voltage control circuit segments the power distribution according to test information identifying defective cells, allowing independent voltage management for each sub-array. This segmentation enables selective application of higher voltage only to sub-arrays containing defective cells.
2Use of energy by moving object
If a lower retention voltage level is applied to reduce power consumption, then power efficiency is improved, but data integrity deteriorates for defective cells
Solution Approach 1:
The patent implements local quality differentiation by applying lower retention voltage levels to sub-arrays without defective cells, improving power efficiency for the majority of the memory. Simultaneously, higher retention voltage levels are applied specifically to sub-arrays containing defective cells to maintain their data integrity. This resolves the contradiction by optimizing power consumption without sacrificing reliability where needed.
Solution Approach 2:
The system uses test information about defective cells to automatically configure retention voltage levels for each sub-array without external intervention. The voltage control circuit self-adjusts the retention voltage based on stored test data, enabling defective sub-arrays to receive appropriate protection while non-defective sub-arrays operate at lower power levels.
3Device complexity
If uniform retention voltage is applied to all sub-arrays, then device complexity is reduced, but power efficiency deteriorates due to unnecessary high voltage application
Solution Approach 1:
The patent performs preliminary testing and characterization of each sub-array during manufacturing to identify defective cells. Test information about voltage sensitivities and defective cell locations is stored in non-volatile memory before the memory enters operation. This preliminary action enables the voltage control circuit to implement differentiated retention voltage levels without adding significant operational complexity, as the configuration is predetermined.
Solution Approach 2:
The patent introduces an intermediary voltage control circuit that mediates between the power supply and the memory sub-arrays. This intermediary component uses stored test information to selectively apply different retention voltage levels to different sub-arrays. While this adds some circuit complexity, it enables significant power savings by avoiding unnecessary high voltage application to non-defective sub-arrays.
Data Source
AI summary
An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.