Volatile Memory Retry-Read Data Accuracy Control

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Solution Overview

Problem

Volatile memory modules often encounter access errors during data retrieval, leading to a mixture of old and new data when retry-read operations are performed, which affects data accuracy and stability.

Innovation Solution

A data retry-read method that involves detecting a notification signal from the volatile memory module, instructing it to execute N command sequences in a buffer, and then sending a read command sequence to retrieve the latest data from specific physical addresses, ensuring that only the latest data is read.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory controller instructs the volatile memory module to re-execute previously executed operation commands when an access error occurs, then the work that has not been completed can be completed, but the read data includes a mixture of both old and new data

Engineering Contradiction:
Improveoperation stabilityVSAvoiddata accuracy
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The memory controller records the command sequence information (including physical addresses and command types) in a buffer before executing the retry-read operation. This preliminary recording allows the controller to identify which data may be mixed and selectively invalidate only those specific addresses, rather than invalidating all cached data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of treating all cached data uniformly, the patent applies selective invalidation based on the specific command sequence being re-executed. The memory controller identifies and invalidates only the data at physical addresses involved in the retry-read operation, leaving other cached data intact. This localized approach maintains data accuracy while preserving the benefits of caching.

Inventive Principle:
Principle #3Local quality

2Productivity

If the memory controller performs retry-read operations to complete unfinished work, then operational continuity is maintained, but data access performance deteriorates due to mixed old and new data

Engineering Contradiction:
Improveoperational continuityVSAvoiddata access performance
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent selectively discards (invalidates) only the specific data entries that correspond to the physical addresses involved in the retry-read command sequence. After the retry operation completes, the memory controller recovers performance by allowing subsequent reads from valid cached data to proceed without accessing the memory module, thus maintaining operational continuity while preserving data access speed.

Inventive Principle:
Principle #34Discarding and recovering

3Speed

If the memory controller reads data from the volatile memory module without validation, then data access speed is maintained, but the occurrence of mixed old and new data increases

Engineering Contradiction:
Improvedata access speedVSAvoiddata accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The memory controller uses feedback from the recorded command sequence information to determine which cached data entries are valid and which should be invalidated. By comparing the physical addresses in the retry-read command sequence with the cached data addresses, the controller provides feedback to selectively invalidate only the problematic entries, maintaining both speed and accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11977745B2Data retry-read method, memory storage device, and memory control circuit element
Publication Date: 2024.05.07 PHISON ELECTRONICS
  • US11977745B2 patent drawing
  • US11977745B2 patent drawing
  • US11977745B2 patent drawing

AI summary

A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.