Volatile Memory Sleep Mode Parity Error Correction
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Solution Overview
Problem
Volatile memory circuits face challenges in reducing power consumption while maintaining data integrity during sleep mode, as they are prone to errors when the supply voltage is lowered, and existing error correction techniques can be latency-prohibitive.
Innovation Solution
Implementing forward error correction (FEC) codes to generate and store parity data, allowing the volatile memory circuit to operate at a lower supply voltage in sleep mode and correct errors upon activation, using a higher-latency high-error-rate FEC code to recover from a larger number of errors introduced during sleep, while employing a lower-latency low-error-rate FEC code in active mode for reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage is reduced to lower power consumption in sleep mode, then power consumption is reduced, but data integrity deteriorates due to error introduction
Solution Approach 1:
Parity data is generated and stored in advance for data blocks before the memory enters sleep mode. This preliminary preparation enables error detection and correction to be performed efficiently when the memory wakes up, allowing the system to tolerate lower supply voltages during sleep mode without compromising data integrity.
Solution Approach 2:
Parity data acts as an intermediary mechanism between the volatile memory and the error correction process. The parity data stored externally allows the memory system to detect and correct errors that occur during low-voltage sleep mode operation, mediating between the conflicting requirements of low power consumption and data reliability.
2Reliability
If a high-error-rate FEC code is used to correct more errors from sleep mode, then data integrity is improved, but latency increases
Solution Approach 1:
The system dynamically adapts its error correction strategy based on operational mode. A high-error-rate FEC code is used when waking from sleep mode to correct accumulated errors, while a lower-latency approach is used during active mode operations. This dynamic adaptation allows the system to optimize between error correction capability and latency depending on the operational context.
Solution Approach 2:
Parity data is prepared in advance for high-error-rate correction, allowing the intensive correction process to occur once during mode transition rather than repeatedly during active operation. This preliminary preparation reduces the overall latency impact of using high-error-rate correction codes.
Data Source
AI summary
Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.