Volatile Memory Word Line Voltage Control for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory devices experience significant leakage current and high active standby current (IDD3N) due to the nature of their operation, which affects their efficiency and power consumption.
Innovation Solution
The implementation of a volatile memory device with a row decoder and column decoder configuration that applies specific voltage levels to word lines during active and precharge periods, reducing leakage current and IDD3N by managing the voltage levels effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the row decoder is activated to perform memory operations, then data access functionality is improved, but leakage current and IDD3N increase
Solution Approach 1:
The patent applies dynamic voltage adjustment to the selected word line based on the operation phase. During the precharge phase, a first voltage level is applied to the selected word line, and during the active operation phase, a second voltage level (different from the first) is applied. This dynamic voltage switching reduces leakage current while maintaining operational functionality, directly resolving the contradiction between data access capability and energy loss.
2Reliability
If voltage is continuously applied to maintain memory cell state, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic voltage application to the selected word line, switching between a first voltage level during precharge and a second voltage level during active operations. This periodic voltage control ensures data retention is maintained during critical phases while reducing unnecessary power consumption during other phases, resolving the contradiction between reliability and energy usage.
Data Source
AI summary
There are provided a volatile memory device, and an operating method. The volatile memory device includes: a plurality of memory cells arranged in rows and columns and structured to store data; word lines; bit lines; a row decoder; a column decoder; and a control logic coupled to communicate with the row and column decoders and configured to, in an active period, provide the row decoder with a first command, and provide the column decoder with a second command, wherein the row decoder is further configured to: apply a first word line voltage higher than a ground voltage to a selected word line, from when the first command is provided; and for a duration over which the row decoder is activated, apply either a second word line voltage lower than the first word line voltage to the selected word line or no voltage to the selected word line.