Volatile Memory Write Buffering for Data Security

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Solution Overview

Problem

Existing memory systems face data loss during reinitialization due to the temporary storage of data in buffer registers, which is not written to memory until a subsequent write instruction, leading to potential data loss during system resets.

Innovation Solution

A method and integrated circuit configuration that systematically record data to be written in a buffer register and write it to memory only when no further write or read requests are received, ensuring data security and time efficiency in successive write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is stored in a buffer register before writing to memory, then data preparation time is reduced, but data loss occurs during system reset

Engineering Contradiction:
Improvedata preparation speedVSAvoiddata security during reset
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by calculating the error-correcting code in advance during the data preparation phase, before the actual write operation to memory. This allows the ECC to be ready and stored in the buffer register ahead of time, so that when a reset occurs, the prepared data with its ECC is already secured in the buffer rather than being lost. The key insight is performing the ECC calculation and preparation work before the critical write moment, thus protecting against reset-induced data loss while maintaining fast write performance.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data is written immediately to memory, then data security is improved, but write latency increases in successive write operations

Engineering Contradiction:
Improvedata securityVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary preparation of the data including ECC calculation and stores it in the buffer register in advance. This preliminary action allows subsequent write operations to simply transfer data from the buffer to memory without repeating the ECC calculation, thus reducing write latency for successive writes while ensuring data security through the pre-calculated ECC protection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer register serves as an intermediary between the data preparation logic and the memory write operation. It temporarily holds the prepared data with ECC, allowing the system to decouple the data preparation phase from the actual write phase. This intermediary buffer enables optimized write timing and reduces latency by preparing data ahead of time without compromising data security, as the ECC-protected data resides in the buffer until written.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If ECC is calculated for each write operation, then error correction capability is maintained, but processing time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The ECC calculation is performed as a preliminary action during the data preparation phase, which occurs before the actual memory write operation. By calculating the ECC in advance and storing it in the buffer register along with the data, the system maintains full error correction capability while optimizing the write operation itself to be faster, as the ECC is already computed and ready.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the data preparation and ECC calculation into a single integrated phase that occurs before the write operation. Rather than treating ECC calculation as a separate post-write step or a bottleneck during the write phase, the system combines these functions in the preparation stage, allowing the ECC-protected data to be staged in the buffer register ready for efficient transfer to memory.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3826015B1Method for writing in a volatile memory and corresponding integrated circuit
Publication Date: 2023.03.29 STMICROELECTRONICS (ROUSSET) SAS
  • EP3826015B1 patent drawingFigure 1
  • EP3826015B1 patent drawingFigure 2
  • EP3826015B1 patent drawingFigure 3

AI summary

The process of writing to volatile memory (MEM) includes at least one reception of a write request to memory, and, in response to each write request to memory (RQ_ECR): - a preparation of the data to be written to memory (PREP_DatEcc) including a calculation of an error-correcting code (ECC); - a recording in a buffer register (BUF_DatEcc) of the data to be written to memory (MEM); and - if no new write or read request to memory (MEM) is received (rq_nok) after said recording (BUF_DatEcc), a writing to memory (MEM) of the data to be written recorded in the buffer register (ECR_DatEcc).