Volatile Buffer for NAND Read Disturb Mitigation

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Solution Overview

Problem

NAND flash memory experiences performance degradation and data corruption due to intensive read workloads, leading to read disturb errors and uncorrectable errors, which are not effectively addressed by existing technologies.

Innovation Solution

A method and storage device that utilizes volatile memory to allocate a buffer when read disturbances exceed the maximum read limit of NAND flash memory blocks, thereby preventing data loss and optimizing read performance without throttling read commands from host devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read operations are performed intensively on NAND flash memory blocks, then data access speed and productivity are improved, but read disturb errors and data corruption increase

Engineering Contradiction:
Improveread access speedVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary actions by monitoring read counts on NAND flash blocks and proactively detecting when read disturb errors occur before they cause uncorrectable data corruption. When a read disturb error is detected, the system preemptively relocates data from affected blocks to safe storage locations, preventing future data loss while maintaining high read performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system introduces an intermediary mechanism - a read disturbance detection and management system that acts as a mediator between intensive read operations and data storage. This intermediary monitors read patterns, detects errors, and manages data relocation transparently, allowing high-speed reads to continue while protecting data integrity through error detection and corrective relocation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error correction codes are used to prevent data corruption, then data reliability is improved, but processing overhead and device complexity increase

Engineering Contradiction:
Improvedata integrityVSAvoiderror correction overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of applying full error correction codes to all data, the system uses partial action by monitoring read counts and selectively applying error detection and relocation only to blocks that show signs of read disturb errors. This selective approach provides sufficient protection against data corruption while minimizing the processing overhead and complexity associated with comprehensive error correction

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If read commands are throttled to prevent read disturb errors, then data reliability is improved, but read performance and productivity deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidread access speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system extracts problematic data from NAND flash blocks that are experiencing read disturb errors and relocates it to safe storage locations. By taking out the affected data and separating it from the intensive read workload, the system prevents data corruption without needing to throttle read commands, thereby maintaining high read performance while ensuring data reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP4075284B1Method and storage device for improving memory performance for intensive read workloads
Publication Date: 2024.12.11 SAMSUNG ELECTRONICS CO LTD
  • EP4075284B1 patent drawingFigure 1
  • EP4075284B1 patent drawingFigure 2
  • EP4075284B1 patent drawingFigure 3

AI summary

A method for reading data in a storage device is provided. The method includes receiving a read command from a host device, wherein the read command indicates stored data in the storage device and a Logical Block Address (LBA) of the stored data; obtaining a Physical Block Number (PBN) based on the LBA and a Logical to Physical (L2P) mapping; determining whether the PBN corresponds to a volatile memory of the storage device; reading the stored data directly from the volatile memory based on the PBN corresponding to the volatile memory; incrementing a read counter associated with the PBN based on the stored data being read directly from the volatile memory; and reading the stored data from a non-volatile memory of the storage device based on the PBN not corresponding to the volatile memory.