Volatile Parity Buffer for NAND Memory Capacity Recovery
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Solution Overview
Problem
Conventional parity protection schemes for NAND memory systems face performance degradation and capacity loss due to the need to store permanent parity data on non-volatile memory, leading to over-provisioning and increased overhead.
Innovation Solution
A parity data protection design that accumulates parity data in volatile SRAM for groups of access lines, discarding it after successful programming without errors, and using it to recover from program fails and uncorrectable errors, eliminating the need for permanent parity data storage on NAND memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If permanent parity data is stored on NAND memory, then error correction capability is improved, but memory capacity is reduced and over-provisioning increases
Solution Approach 1:
The patent introduces volatile memory (SRAM or buffer memory) as an intermediary storage medium for parity data. Instead of permanently storing parity data on NAND memory, the system uses volatile memory as a temporary holding area during programming operations. This intermediary approach allows the system to maintain error correction capabilities while avoiding permanent capacity loss on the NAND memory array.
Solution Approach 2:
The patent employs temporary, disposable parity data storage in volatile memory that is discarded after each programming operation. The parity data in volatile memory is transient and does not need to persist permanently, allowing the system to use low-cost volatile storage rather than consuming valuable non-volatile NAND capacity for parity information.
2Reliability
If permanent parity data is stored on NAND memory, then data integrity is improved, but programming overhead and performance degradation increase
Solution Approach 1:
The patent segments the parity data storage function into separate volatile memory regions for different groups of access lines. By dividing the parity data into multiple segments stored in volatile memory, the system can manage parity information more efficiently during programming operations, reducing the overhead associated with reading and writing permanent parity data to NAND memory.
Solution Approach 2:
Volatile memory serves as an intermediary that temporarily holds parity data during programming operations, eliminating the need to repeatedly read and write permanent parity data from NAND memory. This intermediary storage layer significantly reduces programming overhead and improves performance by avoiding slow NAND access operations for parity data management.
3Reliability
If over-provisioning is increased to store parity data, then error correction capability is improved, but usable memory capacity is reduced
Solution Approach 1:
The patent uses volatile memory as an intermediary storage medium for parity data, which does not consume NAND memory capacity. This approach maintains full usable capacity of the NAND memory array while still providing error correction capabilities through temporary parity storage during programming operations.
Solution Approach 2:
The patent changes the storage parameter of parity data from permanent non-volatile storage to temporary volatile storage. This parameter change allows the system to maintain error correction functionality without permanently allocating NAND capacity for parity data, thereby maximizing usable memory capacity.
Data Source
AI summary
A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.