Volatile Shadow Memory Write Caching for Non-Volatile Storage
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Solution Overview
Problem
Conventional network systems face limitations such as signal degradation, high-level processor requirements, bulky device interfaces, slow data rates, and lack of time-determinism, which restrict miniaturization and data transmission efficiency in applications like aerospace and automotive systems.
Innovation Solution
The implementation of a digital network structure and protocol that uses a low-level instruction set, allowing for precision timing and efficient data acquisition, along with a device interface that accesses non-volatile memory through a volatile shadow memory to enhance data availability and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile memory is accessed directly through the network bus, then data persistence is ensured, but data transmission speed is limited by the memory's slower access time
Solution Approach 1:
The patent introduces a volatile shadow memory as an intermediary between the non-volatile memory and the network bus. The shadow memory stores copies of data from non-volatile memory, allowing fast access to frequently used data while the non-volatile memory maintains data persistence. This mediator resolves the speed-persistence contradiction by enabling rapid data transmission from the shadow memory while the non-volatile memory ensures reliability.
Solution Approach 2:
The system pre-loads data from non-volatile memory into the volatile shadow memory before it is needed for network transmission. By preparing data in advance in the faster volatile memory, the system eliminates wait times during actual data transmission operations, thus improving speed without compromising the persistence ensured by non-volatile memory.
2Adaptability or versatility
If high-level processors are used to handle complex communication protocols, then communication capability is improved, but device size increases and miniaturization is limited
Solution Approach 1:
The patent replaces high-level general-purpose processors with a low-level instruction set architecture that is specifically optimized for the communication protocol. This substitution eliminates the need for complex processing hardware, enabling miniaturization while maintaining full communication capability through streamlined, purpose-built instruction execution.
Solution Approach 2:
The system changes the operational parameters of the processor by using a low-level instruction set with fixed, optimized operations rather than high-level variable instructions. This parameter change allows the device to maintain complex communication capabilities with significantly reduced hardware resources, enabling smaller device size.
3Adaptability or versatility
If complex communication protocols are implemented, then network functionality is enhanced, but data transmission overhead increases and latency increases
Solution Approach 1:
The patent changes the protocol parameters by implementing a low-level instruction set that minimizes overhead bytes and simplifies message structures. This parameter optimization reduces the time required for protocol processing and data transmission, lowering latency while preserving essential network functionality through carefully designed core operations.
4Reliability
If non-volatile memory is used for data storage, then data persistence is ensured, but data access speed is slower compared to volatile memory
Solution Approach 1:
The volatile shadow memory acts as an intermediary cache between the non-volatile memory and the processing units. It stores frequently accessed data copies, providing fast access speeds for operational data while the non-volatile memory maintains the master copy for persistence. This intermediary layer resolves the speed-persistence tradeoff by serving different functions for different data access patterns.
Solution Approach 2:
The system performs preliminary data loading by copying data from non-volatile memory to volatile shadow memory in advance of actual access needs. This pre-positioning of data in faster memory eliminates access delays during critical operations, achieving high speed without sacrificing the persistence guarantees of non-volatile memory.
Data Source
AI summary
An apparatus is provided that includes a non-volatile (device storage) memory configured to store data in a plurality of locations. The apparatus also includes a device interface coupled to the non-volatile memory and including a volatile (device storage) shadow memory configured to store an image of the plurality of locations of the non-volatile memory in a corresponding plurality of locations of the volatile shadow memory. The device interface is configured to receive a command across a network bus from a bus controller, and in response thereto, the device interface is configured to write data from the network bus to a location in the non-volatile memory. This write includes the device interface being configured to write the data to the corresponding location in the volatile shadow memory, and thereafter write the data from the corresponding location in the volatile shadow memory to the location in the non-volatile memory.