Voltage Binning via Functional Path Delay Testing
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Solution Overview
Problem
Current methods of performance-based binning of integrated circuits are placement-dependent and can misrepresent actual performance, leading to incorrect power usage and performance predictions.
Innovation Solution
A method involving functional path testing, where the integrated circuit chip is tested across multiple voltage bins and paths to accurately determine its voltage bin based on performance, ensuring accurate power-to-performance ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If test structures are placed in various positions in the integrated circuit, then binning can be performed, but the results are placement dependent and misrepresent actual performance
Solution Approach 1:
The patent introduces path delay values as an intermediary measurement that accurately reflects the actual signal propagation characteristics of the integrated circuit. Instead of relying on test structure placement, the methodology uses measured path delays between flip-flops to determine binning, providing a mediator that truthfully represents circuit performance regardless of physical test structure locations.
Solution Approach 2:
The patent changes the measurement parameter from test structure response characteristics to actual path delay values between flip-flops. By measuring and using the actual time delays along data paths in the circuit, the methodology transitions from placement-dependent measurements to placement-independent performance characterization, accurately capturing the true operational characteristics of the integrated circuit.
2Productivity
If voltage binning is performed based on placement-dependent test results, then binning can be completed, but power usage is higher than predicted and performance is lower than expected
Solution Approach 1:
The patent replaces the mechanical/test-structure-based binning system with an electrical characterization system that measures actual path delays and power consumption characteristics. By substituting physical test structure responses with electrical measurements of signal propagation delays and associated power usage, the methodology achieves accurate prediction of power-to-performance ratios for voltage binning decisions.
Solution Approach 2:
The patent implements feedback by measuring actual path delay values and using them to determine the appropriate voltage bin assignment. The methodology continuously refines binning decisions based on measured performance data, ensuring that chips are assigned to voltage bins that accurately reflect their power-to-performance characteristics, thereby improving prediction reliability.
Data Source
AI summary
A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.