Voltage Boost Circuit Using MOSFET Well-Substrate Junctions
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Solution Overview
Problem
Conventional voltage boost circuits for integrated circuits (ICs) often overstress active devices by applying voltages exceeding their maximum ratings, which can degrade their long-term reliability.
Innovation Solution
A voltage boost circuit that uses MOSFETs with well-substrate junctions to tolerate boosted voltages, where only the MOSFET well-substrate junctions are subjected to voltages above or below the supply voltages, and a capacitance is used to shift node voltages, with a clock signal toggling between two voltages to charge and discharge the output node, ensuring that no active devices are overstressed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional voltage boost circuits use standard MOSFET devices to generate voltages above supply voltages, then voltage boosting is achieved, but the MOSFETs are overstressed and their long-term reliability degrades
Solution Approach 1:
The patent applies local quality by connecting the bulk terminals of MOSFETs to the output node, creating a localized configuration where only specific junctions (well-substrate) are exposed to high voltages. This selective exposure allows different parts of the device to handle different voltage levels, with the well-substrate junction being the only element subjected to voltages exceeding the supply voltage, thereby protecting other sensitive MOSFET regions from overstress.
2Power
If the drain of the level shifter FET is toggled between ground and increased supply voltage, then voltage multiplication is achieved, but the FET must be specially designed to withstand the larger voltage, increasing device complexity
Solution Approach 1:
The patent uses local quality by configuring the bulk terminal connection specifically for the voltage multiplier MOSFETs. Instead of requiring all MOSFETs to be specially designed for high voltage, only the well-substrate junctions are exposed to high voltages through the bulk connection to the output node. This allows standard MOSFET designs to be used while achieving the voltage boosting function.
Solution Approach 2:
The bulk terminal acts as an intermediary element that mediates the voltage stress distribution. By connecting the bulk terminal to the output node, the patent creates an intermediate reference point that allows the MOSFET to handle high voltages through its well-substrate junction without requiring the entire device to be specially designed for high voltage operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively generates voltages above and below the IC's supply voltages without overstressing any active devices, ensuring robust operation and extended reliability by limiting the stress to the well-substrate junctions of the MOSFETs.
Implementation Method 1
A voltage boost circuit is presented which overcomes the problems noted above, enabling the generation of voltages both above and below an IC's available supply voltages, without overstressing any of the IC's active devices. The present voltage boost circuit comprises a capacitance used to shift a node voltage above the positive supply voltage and/or below the negative supply voltage.
Data Source
AI summary
A voltage boost circuit is driven with a clock signal CLK which toggles between voltages V1 and V2. A first MOSFET is coupled between CLK and an output node OUT, and at least one additional MOSFET is coupled between OUT and a supply voltage. The first terminal of a capacitance is coupled at its first terminal to OUT, and at its second terminal to a delay circuit arranged to toggle its output to ˜V2 or ˜V1 a predetermined amount of time after the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2 or ˜V1, respectively. The capacitance is charged to ˜V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ˜V2. The only active device junctions subjected to the boosted voltage are MOSFET well-substrate junctions, such that no active devices are overstressed.