Voltage Booster for ESD Protection Circuit Clamp Current

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Solution Overview

Problem

Conventional electrostatic discharge (ESD) protection circuits in integrated circuits often suffer from reduced clamp current due to large parasitic resistances between components, which can lead to inadequate protection against ESD events.

Innovation Solution

Incorporating a voltage booster between the trigger output and the control terminal of the shunt transistor to boost the shunt control voltage, thereby increasing the clamp current and improving ESD protection performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection circuits are used with standard trigger output voltage, then the circuit structure remains simple, but the clamp current is reduced due to large parasitic resistances leading to inadequate ESD protection

Engineering Contradiction:
ImproveESD protection effectivenessVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A voltage booster circuit is introduced as an intermediary component between the trigger output and the shunt transistor control terminal. This booster amplifies the trigger output voltage to overcome the voltage drop caused by parasitic resistances, ensuring sufficient gate-source voltage is applied to the shunt transistor to maintain high clamp current during ESD events, thereby resolving the contradiction between protection effectiveness and circuit simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The voltage booster dynamically changes the voltage parameter at the shunt transistor control terminal by amplifying the trigger output voltage. This parameter change compensates for the voltage loss across parasitic resistances, allowing the shunt transistor to operate at optimal clamp current levels even in the presence of large parasitic resistances, thus improving ESD protection effectiveness without requiring complete redesign of the circuit topology

Inventive Principle:
Principle #35Parameter changes

2Reliability

If larger shunt transistors are used to increase clamp current, then ESD protection is improved, but the area occupied by the protection circuit increases

Engineering Contradiction:
Improveclamp currentVSAvoidprotection circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By changing the voltage parameter through the booster circuit, the shunt transistor can achieve higher clamp current with a smaller device area. The boosted voltage ensures full enhancement of the shunt transistor channel, allowing compact transistor dimensions while maintaining high current capability, thus resolving the contradiction between clamp current and circuit area

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The protection function is segmented into two independent stages: the trigger stage that detects ESD events and the voltage booster stage that amplifies the control signal. This segmentation allows the shunt transistor to be optimized for minimum area while the booster provides the necessary voltage drive, separating the detection function from the current drive function and enabling area-efficient design

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The boosted shunt control voltage enhances ESD protection by increasing the clamp current, reducing voltage stress on pads and improving protection margins, while allowing for potentially smaller shunt transistors.

Implementation Method 1

Incorporating a voltage booster between the trigger output and the control terminal of the shunt transistor to boost the shunt control voltage, thereby increasing the clamp current

Methodology Applied
Scientific EffectVoltage boosting:

Implementation Method 2

An integrated circuit (IC) comprising sensitive internal circuitry may be subjected to an Electrostatic Discharge (ESD) event consisting of a very high voltage applied to pins or pads of the circuit

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 3

Input node N1 is coupled to the pad P0 and to the supply rails PSR, GSR via diodes D1, D2 respectively. As diodes D1, D2 are on the ESD discharge path, they are relatively large

Methodology Applied
Scientific EffectDiode conduction: Diode

Implementation Method 4

The trigger 2 comprises a resistor R1 and a capacitor C1 in series forming an RC transient filter

Methodology Applied
Scientific EffectRC filtering: Filter (electronic)

Data Source

PatentUS8995101B2Electrostatic discharge protection circuit
Publication Date: 2015.03.31 STMICROELECTRONICS (ROUSSET) SAS
  • US8995101B2 patent drawing
  • US8995101B2 patent drawing
  • US8995101B2 patent drawing

AI summary

An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage.