Voltage-Domain Buffer Circuit for Low-Leakage Level Shifting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As IC chip components shrink to smaller dimensions, they require lower operating voltages, but still need to interface with external devices at higher voltages, posing a challenge in signal transformation while maintaining signal integrity and protecting core components from over-driving voltage.
Innovation Solution
An input buffer circuit with a combination of inverters, tracking high and low circuits, and feedback loops is used to convert input signals from a higher voltage domain to a lower voltage domain, utilizing PMOS and NMOS transistors biased in suitable voltage domains to achieve efficient signal transformation and reduce leakage currents and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If core components are scaled down to smaller dimensions, then speed and cost are improved, but operating voltage must be scaled down which limits interface capability with external devices
Solution Approach 1:
The buffer circuit is divided into multiple functional blocks: a first buffer for voltage level conversion, a second buffer for signal conditioning, and a third buffer for output driving. This segmentation allows each block to operate in its optimal voltage domain while collectively achieving both high-speed performance and external interface capability.
Solution Approach 2:
The patent introduces an intermediate voltage domain buffer circuit that acts as a mediator between the low-voltage core components and high-voltage external interfaces. This intermediate buffer converts signals from the external high-voltage domain to the internal low-voltage domain, enabling communication without direct connection between incompatible voltage domains.
2Reliability
If input buffer transforms external high-voltage signals to internal low-voltage signals, then signal integrity is maintained, but leakage current increases
Solution Approach 1:
The buffer circuit employs dynamic threshold voltage adjustment through body biasing techniques. The threshold voltages of transistors are dynamically adjusted based on the operating conditions to minimize leakage current while maintaining proper signal transformation. This dynamic adjustment allows the circuit to adapt to varying voltage domains without excessive leakage.
Solution Approach 2:
The patent changes key parameters including transistor threshold voltages, channel lengths, and width-to-length ratios to optimize the balance between signal integrity and leakage current. By carefully selecting these parameters for each buffer stage, the circuit achieves reliable voltage level conversion while minimizing energy loss through leakage.
3Adaptability or versatility
If traditional buffer circuits are used for voltage transformation, then signal conversion is achieved, but power consumption is high
Solution Approach 1:
The buffer circuit utilizes periodic switching of transistor gates to achieve voltage level conversion during specific phases of the signal cycle. By confining active current flow to necessary time windows and putting transistors in high-impedance states during other phases, the circuit reduces average power consumption while maintaining transformation capability.
Solution Approach 2:
The patent employs multiple buffer stages with progressively smaller drive strengths. The first buffer handles the heavy voltage transformation task from high to low voltage domain, while subsequent buffers with reduced drive strength maintain signal integrity with lower power consumption. This hierarchical approach replaces a single high-power buffer with a series of lower-power stages.
Data Source
AI summary
A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generates an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain.