Voltage Generating Circuit for Fast Nonvolatile Memory Writes

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Solution Overview

Problem

Next-generation memory technologies face challenges in achieving high operation speed while maintaining nonvolatile characteristics, as existing solutions like DRAM are volatile and flash memory operates at lower speeds with limited random access.

Innovation Solution

A voltage generating circuit comprising a voltage supplying circuit and a current biasing circuit, which supplies power and controls bias current to optimize voltage levels for rapid output voltage stabilization, and a nonvolatile memory apparatus with bit line and word line control circuits that manage voltages for read and write operations, utilizing transistors to enhance drivability and power efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flash memory is used to achieve nonvolatile characteristics, then data retention without power is improved, but operation speed deteriorates

Engineering Contradiction:
Improvedata retentionVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The voltage generating circuit is divided into two independent circuits: a voltage supplying circuit for rapid voltage generation and a current biasing circuit for precise current control. This segmentation allows each circuit to be optimized independently - the voltage supplying circuit uses transistors configured for fast switching and voltage generation, while the current biasing circuit uses transistors configured for stable current control, thereby achieving both high speed and data retention capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The voltage supplying circuit generates the required voltage levels in advance before the memory write operation begins. By pre-generating the voltages needed for the memory cell, bit line, and word line, the circuit eliminates voltage generation delays during the actual write operation, thereby improving operation speed while maintaining the voltage levels needed for reliable data storage

Inventive Principle:
Principle #10Preliminary action

2Speed

If voltage levels are increased to improve write speed, then operation speed is improved, but power consumption increases

Engineering Contradiction:
Improvewrite speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The current biasing circuit dynamically adjusts the bias current based on the operational state of the memory device. During write operations, the circuit provides higher current to enable fast voltage transitions and rapid data writing. During read operations or idle states, the circuit reduces the bias current to minimize power consumption. This dynamic current adjustment allows the system to achieve high write speeds when needed while consuming less power during normal operation

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes the bias current parameter based on the operational mode. By adjusting the bias current level according to whether the memory is performing read, write, or idle operations, the system optimizes the balance between speed and power consumption. Higher current is applied only when fast writing is required, while lower current is used during other operations to reduce power consumption

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11189324B2Voltage generating circuit and a nonvolatile memory apparatus using the voltage generating circuit
Publication Date: 2021.11.30 SK HYNIX INC
  • US11189324B2 patent drawing
  • US11189324B2 patent drawing
  • US11189324B2 patent drawing

AI summary

A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.