Voltage Clamp Circuit for High-Speed Semiconductor Switching
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Solution Overview
Problem
Existing voltage clamp circuits face challenges in accurately measuring dynamic on-resistance of high-speed semiconductor switching elements due to distortion of amplifier characteristics, parasitic capacitance issues, and time delays, which affect measurement accuracy and speed during high-speed operations.
Innovation Solution
A voltage clamp circuit utilizing a current mirror circuit with high-voltage diodes and a series connection of clamping diodes to maintain current equilibrium, preventing RC time delays and parasitic coupling issues, allowing for accurate voltage measurement across a wide range without affecting operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the voltage measurement range is set to cover high voltage during off-state, then the measurement range is sufficient, but the measurement accuracy of low voltage during on-state deteriorates
Solution Approach 1:
The voltage measurement system is segmented into two parts: a high-voltage measurement path for off-state measurement and a low-voltage measurement path for on-state measurement. The voltage clamp circuit separates the measurement ranges, allowing each path to be optimized for its specific voltage range, thereby resolving the contradiction between measurement range and accuracy.
Solution Approach 2:
The voltage clamp circuit acts as an intermediary between the high-voltage node and the low-voltage measurement system. It clamps the voltage to a safe level during off-state while allowing direct measurement during on-state, enabling the oscilloscope to maintain high accuracy across both voltage ranges.
2Measurement precision
If a voltage clamp circuit is used to limit voltage range, then measurement accuracy improves, but RC time delays and parasitic capacitance cause measurement errors
Solution Approach 1:
The problematic RC time delay and parasitic capacitance are extracted and isolated into a separate voltage clamp circuit that is optimized for clamping function. The measurement path is designed to bypass the clamp's parasitic elements, allowing accurate measurement without the time delays that would affect a directly coupled system.
Solution Approach 2:
The voltage clamp circuit creates a copy of the voltage waveform at a clamped level, allowing the measurement system to observe the voltage transitions without being directly affected by the clamp's parasitic capacitance and time constants.
3Adaptability or versatility
If a normally-on type field-effect transistor is used for voltage clamping, then voltage range limitation is achieved, but parasitic capacitance causes voltage peaks above clamping voltage
Solution Approach 1:
The parasitic capacitance of the normally-on transistor is converted from a harmful factor into a useful feature. During voltage transitions, the parasitic capacitance acts as a charge reservoir that helps maintain current equilibrium and reduces voltage peaks, transforming what was previously a source of measurement error into a stabilizing element.
Solution Approach 2:
The operating parameters of the normally-on transistor are optimized to minimize the negative effects of parasitic capacitance. By adjusting the transistor's bias conditions and selecting appropriate device parameters, the clamping voltage is maintained accurately while the parasitic capacitance effects are reduced to acceptable levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed voltage clamp circuit ensures high-speed operation with accurate voltage measurement and reduced parasitic effects, maintaining current equilibrium and preventing distortion, thus enabling precise characterization of semiconductor switching elements during high-speed transitions.
Implementation Method 1
a circuit for providing at least two currents at its output terminals, at least two diodes each being connected to an output terminal of the circuit for providing at least two currents
Implementation Method 2
at least two diodes each being connected to an output terminal of the circuit for providing at least two currents and further being connected to a line of a ground voltage and the input node respectively
Implementation Method 3
an alternative current path connected to an output terminal of the circuit for providing at least two currents and to a current sinking node, so that the voltage at the input node is reflected as the voltage between two output nodes when the voltage at the input node is lower than a clamping voltage
Data Source
Figure 1
Figure 2~3B
Figure 4
AI summary
A voltage clamp circuit (7) is described for reflecting a voltage at an input node (N1). The voltage clamp circuit (7) comprises a circuit (9) for providing at least two currents (lmir, lref) at its output terminals (OUT1, OUT2). It further comprises at least two diodes (10, 11) each being connected to an output terminal (OUT1, OUT2) of the circuit (9) for providing at least two currents and further being connected to a line of a ground voltage (GND) and to the input node (N1) respectively. It also comprises an alternative current path connected to an output terminal (OUT2) of the circuit for providing at least two currents and to a current sinking node. The voltage clamp circuit thus is configured so that the voltage at the input node (N1) is reflected as the voltage between two output nodes (OUT1, OUT2) when the voltage at the input node is lower than a clamping voltage and so that the voltage is fixed between the two output nodes to the clamping voltage when the voltage at the input node (N1) is higher than the clamping voltage. A corresponding method and corresponding systems using such a voltage clamp circuit are also described.