Voltage Clamping Delay Circuit for Power Supply Variation
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Solution Overview
Problem
Conventional delay circuits in semiconductor applications do not effectively compensate for drastic changes in delay time with varying power supply voltages, leading to inefficiencies in systems like synchronous buck converters, where dead-time increases at lower voltages due to increased propagation delay.
Innovation Solution
A delay circuit with a voltage clamping module that prolongs delay time as power supply voltage decreases, utilizing a CMOS inverter with a load capacitor and a voltage clamping module generating a voltage drop to dynamically adjust delay time, particularly at low power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional CMOS inverter delay circuit is used, then the circuit structure is simple, but the delay time does not vary significantly with power supply voltage changes
Solution Approach 1:
The patent introduces a voltage clamping module that dynamically changes the operating parameters of the inverter by clamping the voltage swing at the inverter output. This voltage clamping creates a non-linear relationship between power supply voltage and delay time, enabling significant delay variation with Vcc changes while maintaining a relatively simple circuit structure based on the existing CMOS inverter framework
2Measurement precision
If a digitally controlled delay circuit with feedback loop is used, then the delay time can be precisely controlled, but the cost is high and the structure is complicated
Solution Approach 1:
The patent extracts and utilizes the inherent non-linear voltage-delay characteristics of the CMOS inverter when operated with voltage clamping. By removing the need for complex digital control logic and feedback loops, the invention achieves adequate delay control precision through the passive voltage clamping mechanism, significantly simplifying the circuit structure while maintaining functional effectiveness
3Use of energy by moving object
If the power supply voltage decreases, then the power consumption is reduced, but the propagation delay of the adaptive gate driving circuitry increases
Solution Approach 1:
The patent converts the harmful effect of increased propagation delay at low voltage into a beneficial feature by intentionally designing the voltage clamping mechanism to exaggerate this effect. The clamping creates a scenario where small voltage drops produce large delay increases, which can be used to compensate for other timing variations in the system, effectively transforming the low-voltage delay penalty into a useful compensation mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases delay time at low power supply voltages, ensuring synchronization of signals across different power supply conditions, thereby optimizing system performance and maintaining a high power supply rejection ratio.
Implementation Method 1
the first voltage clamping generates a voltage drop when a current flows through the first voltage clamping module configured to prolong the delay time of the delay circuit as the power supply voltage decreases
Data Source
AI summary
The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.