Voltage Compensation Line for 3D Nonvolatile Memory Gate Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices with three-dimensional structures face performance degradation due to voltage drop in target gate lines with higher resistance values, leading to increased setup time and reduced operation speed.
Innovation Solution
A nonvolatile memory device design that includes a voltage compensation line and conduction paths to compensate for the driving voltage applied to target gate lines, reducing resistance and enhancing voltage delivery to the end portions of these lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree and memory capacity are increased in three-dimensional nonvolatile memory devices, then the memory capacity is improved, but the operation speed is reduced due to increased signal line load and voltage drop
Solution Approach 1:
A voltage compensation line is introduced as an intermediary element to transfer driving voltage to the target gate line. This compensation line acts as a mediator that supplies additional voltage current to counteract the voltage drop caused by high resistance in the target gate line, thereby maintaining operation speed despite increased integration degree and memory capacity
Solution Approach 2:
The electrical parameters (voltage and current) of the target gate line are dynamically adjusted by introducing a compensation current through the voltage compensation line. By changing the voltage parameter through active compensation, the system offsets the adverse effects of increased resistance from higher integration, thus maintaining operation speed while achieving higher memory capacity
2Quantity of substance
If the integration degree is increased to enhance memory capacity, then the memory capacity is improved, but the voltage drop in target gate lines increases leading to performance degradation
Solution Approach 1:
The voltage compensation line serves as a mediator that introduces compensation current to the target gate line, stabilizing the voltage parameter despite increased resistance from higher integration. This intermediary element ensures reliable voltage delivery to maintain performance in high-capacity memory devices
Solution Approach 2:
The voltage compensation line proactively counteracts the voltage drop before it significantly degrades performance. By introducing compensation current in advance through the compensation path, the system prevents voltage instability that would otherwise occur due to high resistance in densely integrated gate lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces voltage deviations between gate lines, enhancing the performance and operation speed of nonvolatile memory devices by compensating for voltage drops in target gate lines with higher resistance values.
Implementation Method 1
a near conduction path connecting in the second direction the first portion of the voltage compensation line and a near end portion of the target gate line, and a far conduction path connecting in the second direction a second portion of the voltage compensation line and a far end portion of the target gate line
Data Source
AI summary
A nonvolatile memory device includes a plurality of gate lines extending in a first direction and stacked in a second direction to form a memory block, where the second direction is perpendicular to the first direction, an address decoder disposed at a first side of the plurality of gate lines to drive the plurality of gate lines, a voltage compensation line extending in the first direction substantially in parallel with the plurality of gate lines, and overlapping with a target gate line among the plurality of gate lines in the second direction, a rising vertical contact extending in the second direction to connect the address decoder and a first portion of the voltage compensation line, and conduction paths connecting in the second direction the first and second portions of the voltage compensation line with near and far end portions of the target gate line.