Localized Voltage Contrast Scan Layout for Faster Wafer Defect Detection
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Solution Overview
Problem
Current voltage contrast (VC) structures in semiconductor manufacturing require large areas to detect defects, leading to slow defect identification and increased scanning time, which hampers the pace of semiconductor process design and manufacturing.
Innovation Solution
The implementation of localized voltage contrast structures on a wafer substrate with signal and ground terminals, allowing for efficient defect identification by scanning a centralized area, significantly reducing the time required to collect defect data through electron beam inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large area VC structures are used to detect defects, then defect detection coverage is improved, but scanning time increases significantly
Solution Approach 1:
The patent divides the wafer surface into multiple discrete VC structures distributed across different locations. Instead of using one large VC structure, multiple smaller VC structures are segmented and placed throughout the wafer, allowing parallel defect detection across multiple regions simultaneously, thus reducing total scanning time while maintaining comprehensive coverage.
Solution Approach 2:
The patent transitions from a single large-area VC structure to multiple small-area VC structures distributed in space across the wafer surface. This spatial distribution adds a dimensional aspect to defect detection, enabling simultaneous inspection of multiple locations and dramatically reducing the time required to scan the entire wafer area.
2Measurement precision
If large area VC structures are used to detect defects, then defect detection capability is improved, but manufacturing efficiency decreases
Solution Approach 1:
The patent segments the defect detection function into multiple independent VC structures distributed across the wafer. Each VC structure can be inspected independently and simultaneously, enabling parallel processing of defect detection tasks. This segmentation maintains comprehensive defect detection capability while dramatically improving manufacturing efficiency by reducing inspection time and increasing throughput.
Solution Approach 2:
The patent creates an optimized inspection environment by distributing VC structures across the wafer surface, allowing the electron beam inspection system to operate more efficiently. The distributed architecture enables better utilization of inspection resources and reduces idle time, thereby improving overall manufacturing efficiency without compromising defect detection capability.
3Speed
If centralized scan area is used, then scanning speed is improved, but area coverage may be reduced
Solution Approach 1:
The patent segments the inspection area into multiple small VC structures distributed across the wafer surface. Each VC structure is scanned independently in a centralized manner, allowing high scanning speed for each individual structure. The segmentation enables parallel inspection of multiple locations, effectively covering the entire wafer area while maintaining high scanning speed through simultaneous processing of multiple segments.
Solution Approach 2:
The patent resolves the contradiction by adding spatial distribution as an additional dimension. Instead of scanning one large area sequentially, multiple small VC structures are distributed across the wafer in space, allowing the scanner to focus on small centralized areas with high speed while the overall coverage is achieved through the spatial distribution of multiple VC structures across the wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables at least 10 times faster defect data collection and more efficient scanning of VC structures, improving the speed and efficiency of defect identification on semiconductor wafers.
Implementation Method 1
voltage contrast scan area on the wafer substrate for testing defects in the devices
Data Source
AI summary
Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested. During the electronic beam scan, ends of the plurality of traces within the scan area that are coupled with devices that are electrically shorted will appear bright, and those that are electrically open will appear dark. Other embodiments may be described and/or claimed.