Voltage Control Apparatus Stabilizing Output With Inductor Current Feedback
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Solution Overview
Problem
Existing voltage/current regulation circuits using high-side and low-side FETs face instability due to low equivalent series resistance (ESR) in capacitors, leading to output voltage instability, especially in constant on-time operation, where the phase of output voltage lags behind the inductor current, causing unnecessary switching and instability.
Innovation Solution
The solution involves superimposing a voltage proportional to the inductor current on the feedback voltage by multiplying the inductor current with the drain-source resistance of the FETs and an optional gain factor, allowing the comparator to trigger based on this modified signal, thereby ensuring the output voltage is in phase with the inductor current, stabilizing the operation without relying on current emulation or specific inductor ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a capacitor with low equivalent series resistance (ESR) is used, then the circuit operates with reduced power loss and improved efficiency, but the output voltage becomes unstable due to phase lag between output voltage and inductor current
Solution Approach 1:
The patent implements feedback by comparing the inductor current ( sampled at specific timing) with the output voltage and adjusting the FET switching duty cycle accordingly. This closed-loop control compensates for the phase lag caused by low ESR capacitors, maintaining output voltage stability while allowing operation with low-power-loss capacitors
Solution Approach 2:
The patent changes the control parameter from relying on capacitor ESR characteristics to directly sampling and comparing inductor current with output voltage. By modifying the control strategy to account for the actual phase relationship between current and voltage, the system maintains stability regardless of capacitor ESR value
2Productivity
If the circuit operates in constant on-time mode with low ESR capacitors, then the switching frequency is simplified to be fixed, but unnecessary switching occurs and instability arises due to phase lag
Solution Approach 1:
The patent uses feedback comparison between sampled inductor current and output voltage to determine optimal switching timing. This allows the fixed on-time mode to maintain stability by actively compensating for phase lag through real-time voltage comparison, preventing unnecessary switching while preserving the simplicity of fixed-frequency operation
Solution Approach 2:
The patent performs preliminary sampling of the inductor current at a specific timing point before the switching decision is made. This advance sampling allows the control circuit to anticipate the phase relationship and adjust switching timing proactively, preventing instability before it occurs
3Device complexity
If output voltage ripple is used for regulation, then the control mechanism is simple, but the output voltage phase lags behind inductor current causing instability
Solution Approach 1:
The patent implements feedback by directly comparing the sampled inductor current with the output voltage waveform. This simple yet effective feedback mechanism detects the phase relationship and adjusts switching duty cycle to eliminate phase lag, maintaining stability without adding complex control circuitry
Solution Approach 2:
The patent uses the existing output voltage ripple and inductor current waveform themselves as the regulation signals. By comparing these naturally occurring waveforms directly, the system achieves phase synchronization without requiring additional reference signals or complex processing, allowing the circuit to self-regulate based on its own operating characteristics
Data Source
AI summary
A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”.