Voltage-Controlled Delay Buffer With Varactor Tuning

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Solution Overview

Problem

Voltage-controlled delay buffers face challenges in achieving a favorable trade-off between wide tuning range and noise reduction, while also ensuring proper interfacing with preceding and succeeding circuits.

Innovation Solution

A voltage-controlled delay buffer is designed using a cascade topology of inverters, incorporating PMOS and NMOS transistors and varactors, where the delay is controlled by differential voltages, providing shunt capacitance and ensuring symmetrical response to transitions, thus minimizing noise and interface issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If the power supply voltage is reduced to achieve very long delay, then the delay increases, but the output signal becomes highly susceptible to additive noise

Engineering Contradiction:

ImprovedelayVSAvoidnoise susceptibility

Core Design Contradiction:

Duration of action of moving objectVSObject-affected harmful factors

Solution Approach 1:

The delay buffer is divided into multiple stages, each contributing a portion of the total delay. This segmentation allows the system to achieve long total delay without requiring any single stage to operate at extremely low voltages that would cause high noise susceptibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple delay stages are combined in cascade to achieve the total delay. By merging several moderate-delay stages, the system achieves long overall delay while each stage maintains sufficient voltage headroom to operate with low noise susceptibility.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If the power supply voltage is made variable to achieve wide tuning range, then the delay tuning range increases, but the interface with preceding and succeeding circuits deteriorates

Engineering Contradiction:

Improvetuning rangeVSAvoidinterface compatibility

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The control voltage is applied locally to specific control nodes within each delay stage rather than varying the global power supply voltage. This allows delay tuning while maintaining stable power supply levels for proper interfacing with external circuits.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Control nodes within each delay stage act as intermediaries between the control voltage and the signal path. The control voltage modulates the delay through these intermediary nodes without directly varying the power supply voltage, thus maintaining interface compatibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of operation

If a tunable current source is used to control delay, then the delay becomes voltage-controllable, but low-frequency flicker noise is introduced

Engineering Contradiction:

Improvevoltage controlVSAvoidflicker noise

Core Design Contradiction:

Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The problematic tunable current source is extracted and replaced with voltage-controlled switches that modulate pre-charged capacitor discharge. This removes the flicker noise source while retaining voltage controllability of the delay.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The electrical current-based delay control is replaced with a voltage-controlled switching mechanism. Instead of using a tunable current source that generates flicker noise, the patent uses voltage-controlled switches to discharge pre-charged capacitors, achieving voltage control without the harmful noise.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution achieves a wide tuning range with reduced noise susceptibility and maintains interface compatibility, ensuring stable and balanced signal transitions.

Implementation Method 1

a first forward connected varactor and a first backward connected varactor controlled by the first voltage and the second voltage, respectively and configured to provide a shunt capacitance at the input node; and a second forward connected varactor and a second backward connected varactor controlled by the first voltage and the second voltage, respectively and configured to provide a shunt capacitance at the output node

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20220352829A1Voltage-Controlled Delay Buffer Of Wide Tuning Range

Publication Date: 2022.11.03 REALTEK SEMICON CORP

AI summary

A voltage-controlled delay buffer includes a plurality of inverters configured in a cascade topology to receive an input signal from a source circuit and output an output signal to an output circuit. The plurality of inverters includes a voltage-controlled inverter controlled by a control signal having a first voltage and a second voltage. The voltage-controlled inverter includes a PMOS transistor configured to assist a low-to-high transition of an outgoing signal, and an NMOS transistor configured to assist a high-to-low transition of the outgoing signal. Two varactors, one forward connected and the other backward connected are configured to adjust a delay of a transition of an incoming signal.; Another two varactors, one forward connected and the other backward connected, configured to adjust a delay of a transition of the outgoing signal in accordance with the first voltage and the second voltage.