Voltage-to-Delay ADC Circuit with Chopped Residue Conversion
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Solution Overview
Problem
Conventional delay domain analog-to-digital converters face issues with flicker noise, common mode rejection ratio degradation, and increased power consumption due to double differential pairs and parallel TDC paths, which affect the spurious free dynamic range and chip area efficiency.
Innovation Solution
The proposed solution involves a multi-bit input buffer generating differential residues relative to zero-crossing references, with zero-crossing comparators and folding logic to encode a digital output word, eliminating the need for parallel TDC circuitry and reducing flicker noise by chopping the residues rather than the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If double differential pairs are used in conventional delay domain ADCs, then the converter can handle high data rates, but power consumption increases and common mode rejection ratio degrades
Solution Approach 1:
The patent extracts and eliminates the unnecessary double differential pair structure from the conventional delay domain ADC. By using a single differential pair followed by a flash converter, the design removes the redundant second differential stage that was causing excessive power consumption and CMRR degradation, while maintaining the ability to handle high data rates through the flash converter's parallel comparison architecture.
Solution Approach 2:
The patent uses a flash converter to create multiple comparison paths in parallel, effectively copying the comparison function across multiple reference voltages simultaneously. This allows the system to achieve high data rate handling capability without requiring sequential processing through multiple differential stages, thereby reducing power consumption while maintaining speed performance.
2Measurement precision
If parallel TDC paths are implemented to resolve equidistant reference levels, then measurement precision improves, but chip area increases
Solution Approach 1:
The patent merges the functions of multiple parallel TDC paths into a single TDC by using a flash converter to determine the input range zone. The flash converter identifies which reference level zone the input signal falls into, allowing a single TDC to process the signal with full precision, thereby eliminating the need for multiple parallel TDC paths and reducing chip area while maintaining measurement precision.
Solution Approach 2:
The flash converter performs a preliminary classification of the input signal by determining which reference level zone it falls into before the signal is passed to the TDC. This preliminary action allows the single TDC to focus its resolution capability on the specific zone, achieving high measurement precision without requiring multiple parallel TDC paths, thus reducing chip area.
3Speed
If conventional delay domain conversion is used, then the converter operates at high data rates, but flicker noise affects spurious free dynamic range
Solution Approach 1:
The patent replaces the mechanical delay-based conversion process with an electrical field-based flash conversion process. Instead of using time delays and differential pairs that are susceptible to flicker noise, the system uses simultaneous voltage comparisons across multiple reference levels through the flash converter, eliminating the flicker noise mechanism while maintaining high data rate operation through parallel processing.
Solution Approach 2:
The patent introduces periodic chopping of the differential input signal at a frequency higher than the flicker noise bandwidth. This periodic modulation shifts the signal spectrum away from the flicker noise region, allowing the flash converter to operate at high data rates without the flicker noise degrading the spurious free dynamic range, as the noise and signal occupy different frequency bands.
Data Source
AI summary
An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.