Voltage-to-Delay Converter Calibration for Low-Voltage Linearity
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Solution Overview
Problem
Existing delay domain analog-to-digital converters (ADCs) face significant non-linearity issues due to transistor saturation margins at low power supply voltages, leading to compressive gain characteristics that affect the accuracy and performance of high data rate communications devices, particularly in mobile and battery-powered devices like 5G user equipment.
Innovation Solution
A voltage-to-delay converter is implemented with a dynamic amplifier input stage and a constant current discharge stage, where the latter's gain characteristic is calibrated to counteract the non-linearity of the former, using calibration logic to adjust the common mode voltage and discharge current, thereby maintaining transistor saturation and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a dynamic amplifier input stage is used in a voltage-to-delay converter, then the converter can operate at low power supply voltages, but transistor saturation margins are reduced causing non-linearity and compressive gain characteristics
Solution Approach 1:
The patent adjusts the discharge current magnitude as a controllable parameter to compensate for non-linearity. By varying the discharge current, the system maintains transistor saturation margins and achieves linear gain characteristics even at low power supply voltages where traditional designs would fail.
Solution Approach 2:
The system employs feedback mechanisms where the discharge current is dynamically adjusted based on the operating conditions. This feedback loop ensures that transistors remain in saturation region, preventing the compressive gain characteristics that would otherwise occur at low voltages.
2Measurement precision
If the discharge current is increased to maintain transistor saturation, then linearity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the discharge current rather than using a fixed current source. The discharge current is adjusted in real-time based on the input voltage range and operating conditions, allowing the system to maintain optimal linearity while minimizing power consumption during different phases of operation.
Solution Approach 2:
The system changes the discharge current parameter adaptively to match the input signal characteristics. This allows the converter to use higher current only when necessary to maintain saturation and linearity, while using lower current during other periods to reduce overall power consumption.
Data Source
AI summary
A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.