Voltage-Dependent Design Rule Checking for IC Layout Spacing
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Solution Overview
Problem
Conventional design approaches for integrated circuits (ICs) face challenges in accurately determining voltage-based spacing rules, leading to inefficient use of silicon area and signal integrity issues due to overly pessimistic spacing requirements, especially when dealing with multiple voltage domains and complex layout designs.
Innovation Solution
A computer-implemented method and system for Voltage-Based Design Rule Checking (VDRC) in a full-custom EDA platform that automatically determines net voltages through dynamic simulation, allows manual override, and propagates these voltages to the layout and verification tools, enabling context-aware and hierarchical management of voltage information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional design approaches use overly pessimistic minimum spacing rules to ensure signal integrity and prevent dielectric breakdown, then reliability is improved, but silicon area is wasted
Solution Approach 1:
The patent changes the parameter of spacing distance from a fixed pessimistic value to a dynamic value that depends on the actual voltage difference between adjacent nets. By calculating the voltage delta and applying the appropriate spacing rule from a voltage-dependent design rule manual, the system achieves both reliability (by ensuring sufficient spacing when needed) and area efficiency (by allowing closer spacing when voltage differences are small).
Solution Approach 2:
The patent introduces dynamics into the previously static spacing rules by making the spacing requirement dependent on the voltage difference between nets. The verification tool dynamically determines the appropriate spacing based on simulated or measured voltage values, rather than applying a fixed conservative spacing rule to all net pairs.
2Measurement precision
If layout designers manually mark voltage domains to enable accurate voltage-based spacing verification, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements self-service by having the verification tool automatically obtain voltage information from simulation data or measurement without requiring manual intervention from the layout designer. The tool autonomously queries the voltage of each net and performs the voltage-based spacing verification, eliminating the need for designers to manually mark voltage domains while maintaining high measurement precision.
Solution Approach 2:
The patent replaces the manual mechanical process of marking voltage domains with an automated electronic verification process. Instead of physically annotating the layout with voltage domain information, the system uses software to automatically query voltage values and perform comparisons, substituting human labor with automated computational methods.
3Productivity
If static-analysis based approaches propagate net voltages using voltage propagation algorithms, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The patent accepts partial action by using simulation-based voltage values rather than performing complete dynamic analysis. The verification tool uses voltage values from transient or DC simulations, which provide sufficiently accurate voltage information for spacing verification without requiring exhaustive analysis of all possible operating conditions, thus balancing productivity and precision.
Data Source
AI summary
The independent claims of this patent signify a concise description of embodiments. Embodiments described herein are directed to a database-driven scheme for automating the process of VDRC checking in a full-custom EDA Design and Implementation tool. Various embodiments include at least a computer-implemented method of performing Voltage-based Design Rule Checking (VDRC) in a full-custom EDA Design and Implementation Platform is provided, the method comprising receiving a plurality of net voltages from at least a first net and a second net, wherein reception of the plurality of net voltages is from one or more of a simulation, a plurality of simulations, manual override, or direct input, determining a net voltage range, the net voltage range being a difference between a first net voltage of a first net and a second net voltage of a second net, causing transfer of the net voltage range to a layout editing process, the layout editing process resulting in generating a layout, and performing VDRC verification, confirming a VDRC clean layout. This Abstract is not intended to limit the scope of the claims.