Voltage Detecting Circuit Using Transistor Current Matching
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Solution Overview
Problem
Existing voltage detecting circuits are large in size and consume high power due to the necessity of a reference voltage circuit and comparator, which complicates the detection of input voltage exceeding a preset trigger voltage.
Innovation Solution
A voltage detecting circuit utilizing two P-type field-effect transistors (or N-type field-effect transistors) with adjusted gate width and length to equalize current between the source and drain, allowing for simple voltage detection and reduced power consumption, where the second transistor's current is lower when the input voltage is below the trigger voltage and equal or higher when it exceeds the trigger voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference voltage circuit and comparator are used for voltage detection, then the detection accuracy is improved, but the circuit size increases and power consumption becomes large
Solution Approach 1:
The patent extracts and eliminates the reference voltage circuit and comparator from the voltage detection system. Instead of using these complex components, the invention uses a simple transistor-based current comparison method where the detection transistor's current is directly compared with a reference current generated by a current source, achieving voltage detection without the bulky reference voltage circuitry
Solution Approach 2:
The patent changes the detection parameter from voltage comparison (using comparator) to current comparison (using transistor current characteristics). By adjusting the gate voltage of the detection transistor and comparing its drain current with a reference current, the circuit achieves voltage detection functionality through current parameter comparison, simplifying the overall circuit structure
2Measurement precision
If a reference voltage circuit and comparator are used for voltage detection, then the detection accuracy is improved, but the power consumption becomes large
Solution Approach 1:
The patent removes the power-hungry comparator and reference voltage circuit from the detection system. The new design uses transistors operating in saturation mode with controlled gate voltages to perform current comparison, which consumes significantly less power while maintaining detection accuracy
Solution Approach 2:
The patent employs a clock signal to periodically switch the detection transistor between different operating states. The detection transistor is turned on during the active phase to perform current comparison and turned off during the inactive phase, reducing average power consumption while maintaining detection functionality
3Ease of operation
If the gate of the NMOS depletion transistor is connected with the drain and the gate of the NMOS enhancement transistor is connected with the drain, then the circuit operation is simplified, but current continues to flow and power consumption becomes large
Solution Approach 1:
The patent introduces dynamic control of transistor gate voltages through a clock signal. The detection transistor's gate voltage is switched between different levels based on the clock signal phase, enabling the transistor to operate in saturation mode during the active phase and reduce current flow during the inactive phase, thus reducing power consumption while maintaining operational simplicity
Solution Approach 2:
The patent uses periodic clock signal activation to control the detection transistor. The transistor is activated only during specific clock phases to perform detection, and deactivated during other phases to minimize current flow and power consumption, resolving the contradiction between operational simplicity and power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration enables efficient detection of input voltage exceeding the trigger voltage with a simple circuit design and reduced power consumption, achieved by using enhancement type transistors and optionally additional transistors in series to further lower power consumption.
Implementation Method 1
The first transistor is configured as a P-type field-effect transistor, and includes a source connected with the input terminal directly or indirectly, a gate connected with a low voltage input terminal and a drain connected with an output terminal. The second transistor is configured as a P-type field-effect transistor, includes a gate and a source connected with the output terminal respectively and a drain connected with the low voltage input terminal. Gate width and gate length of the second transistor is adjusted so that current between the source and the drain becomes approximately same as current between the source and the drain of the first transistor when the voltage applied to the input terminal reaches the trigger voltage.
Data Source
AI summary
In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.