Voltage Detection Circuit for Power Gated IC Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CMOS logic gates are not suitable for voltage level detection in power gated regions of integrated circuits due to low input threshold voltages and slow voltage rise, leading to unnecessary power consumption and reliability issues.
Innovation Solution
A modified Schmitt trigger circuit with a high programmable input threshold voltage and active pull-down circuit, utilizing PMOS and NMOS transistors, is introduced to detect the voltage level of a switched power supply, with optional NMOS transistors for threshold adjustment, ensuring the output is high only when the input voltage exceeds the operational threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If typical CMOS logic gates are used for voltage detection, then the circuit structure is simple, but the input threshold voltage is too low (1-200 mV) to detect operational voltage levels
Solution Approach 1:
The patent modifies the Schmitt trigger circuit by adding stacked NMOS transistors between the input and VDD, which increases the input threshold voltage from typical CMOS levels (1-200 mV) to operational voltage levels (approximately 80% VDD). This parameter change enables the circuit to detect when the power supply has reached its operational voltage level.
2Productivity
If power is restored quickly to a power gated region, then productivity is improved, but crowbar currents are induced causing power consumption and reliability issues
Solution Approach 1:
The modified Schmitt trigger circuit provides feedback control by monitoring the input voltage and adjusting the output accordingly. The circuit only allows power to be considered restored when the voltage reaches the high threshold level, preventing premature operation that would cause crowbar currents and reliability issues.
3Ease of operation
If the voltage threshold for detection is lowered to match typical CMOS gates, then ease of operation is improved, but power consumption increases due to crowbar currents
Solution Approach 1:
The patent changes the detection threshold parameter from low CMOS levels (1-200 mV) to high operational levels (approximately 80% VDD) by modifying the Schmitt trigger circuit with stacked NMOS transistors. This ensures that power is only considered restored when the voltage reaches a safe level, preventing crowbar currents and excessive power consumption.
Data Source
AI summary
A voltage detector to detect the voltage level of a switched power supply associated with a power gated region of an integrated circuit. The voltage detection circuit, which can be described as a modified Schmitt trigger circuit, comprises PMOS and NMOS transistors, and an added stack of NMOS transistors to set the output to a value of 1 in response to detection of an input voltage at the input greater than an operational voltage of the switched power supply, for example approximately 80% VDD and above. A pull-down circuit actively pulls the circuit output low before the circuit input drops below the low input threshold. Optional additional NMOS transistors provide the capability to adjust the threshold. The voltage detector circuit can be calibrated and used to detect whether or not the switched power supply associated with a power gated design has reached its operational voltage level.