Voltage Discharge Circuit Dividing Current to Prevent Overshoot
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Solution Overview
Problem
Conventional voltage discharge methods for non-volatile memory devices face challenges in accurately discharging high voltages without causing overshoot, which can lead to damage in larger memory arrays with lower over-voltage tolerances, due to the complex balancing of discharge paths and precise timing control required to manage capacitance coupling between memory cell terminals.
Innovation Solution
A voltage discharge system with concurrent first and second discharge paths is established, where the first path is between ground and a node, and the second path is between the nodes, allowing discharge current to be divided between these paths, utilizing current mirrors to maintain balanced discharge rates and reduce overshoot by distributing capacitive discharge currents effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional discharge transistors connect all array terminals to ground simultaneously, then discharge speed is improved, but overshoot occurs causing terminal voltage to exceed safe operating limits
Solution Approach 1:
The discharge path is segmented into two distinct paths: a first discharge path from the positive node to ground, and a second discharge path from the negative node to ground. This segmentation allows independent control of discharge currents, preventing overshoot by ensuring that discharge current is divided between the two paths rather than flowing through a single path, thus resolving the contradiction between fast discharge and overshoot prevention.
2Reliability
If discharge paths are carefully balanced to minimize overshoot, then reliability is improved, but device complexity increases due to precise timing control and transistor strength adjustment requirements
Solution Approach 1:
The patent merges the discharge control into a single unified circuit configuration where the first and second discharge paths are simultaneously activated through a common control mechanism. This eliminates the need for complex timing skew control and individual transistor strength adjustment, as the merged structure naturally divides discharge current between the two paths, reducing device complexity while maintaining reliability.
3Device complexity
If discharge current is directed through a single path, then device complexity is reduced, but overshoot occurs due to capacitance coupling between memory cell terminals
Solution Approach 1:
The discharge path is segmented into two independent paths that simultaneously discharge the positive and negative nodes. This segmentation prevents capacitance coupling from causing overshoot by providing separate current paths, eliminating the need for complex timing control while maintaining simple device structure.
4Object-affected harmful factors
If timing skew between discharge transistor activation is carefully controlled, then overshoot is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The discharge control is merged into a single simultaneous activation mechanism, eliminating timing skew entirely. This approach reduces overshoot without requiring precise timing control, thereby reducing manufacturing precision requirements while maintaining effective overshoot minimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively discharges large arrays without significant overshoot, eliminates critical timing skew requirements, and ensures safe operation by uniformly dissipating energy across all capacitance components, preventing junction forward-biasing and snap-back damage.
Implementation Method 1
Large circuit capacitances, including the capacitance that couples arrays of memory gates to their respective source, drain, and well terminals, thereby charge to voltages that can approach the positive and negative breakdown limits of the IC technology
Implementation Method 2
Concurrent first and second discharge paths are established... Discharge current from the first node is divided between the first discharge path and the second discharge path
Data Source
AI summary
In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.