Voltage Distributor Level Shifter With Single-Clock Pin Reduction
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Solution Overview
Problem
Existing level shifters require two input clock signals, increasing the number of pins needed and potentially reducing the reliability of LCD panels, while also failing to accurately transform voltage levels between external and internal circuits.
Innovation Solution
A level shifter that utilizes only one input clock signal to transform 0-5V voltage levels into 10-10V levels, employing a voltage distributor with transistors and a switch to distribute potential levels and generate an output signal, ensuring reliable operation with fewer pins and wider DC voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two input clock signals are utilized to drive the level shifter, then the voltage level transformation function is achieved, but the number of pins increases and reliability decreases
Solution Approach 1:
The patent merges the functions of two separate clock signals into a single clock signal input. The level shifter circuit processes one clock signal to generate multiple internal clock phases (CLK1, CLK2, CLK3, CLK4) that were previously requiring separate external inputs. This consolidation reduces the pin count from two to one while maintaining the voltage level transformation capability between external (0-5V) and internal (10V/0V) circuits.
2Device complexity
If a level shifter utilizing only one input clock signal is used, then the pin number is reduced, but the level shifter cannot work correctly with 0V and 10V biases
Solution Approach 1:
The patent changes the bias voltage parameters from the conventional -10V/10V configuration to a 0V/10V configuration that is compatible with LCD panel internal circuit biases. By adjusting the bias voltage parameters and redesigning the voltage distributor circuit accordingly, the level shifter achieves correct operation with one clock input under the new bias conditions, resolving the incompatibility issue while maintaining pin reduction benefits.
Solution Approach 2:
The patent introduces a voltage distributor as an intermediary component that adapts the single input clock signal and bias voltages to generate the required multiple internal clock phases. This intermediary circuit enables the level shifter to function correctly with one clock input and 0V/10V biases by providing the necessary voltage distribution and signal conditioning internally, without requiring external -10V bias or multiple clock inputs.
3Adaptability or versatility
If the level shifter uses -10V and 10V biases, then the voltage transformation range is achieved, but it cannot operate correctly with 0V and 10V biases from LCD internal circuits
Solution Approach 1:
The patent modifies the bias voltage parameters from -10V/10V to 0V/10V to match the LCD panel internal circuit biases. This parameter change allows the level shifter to operate correctly with the existing LCD bias voltages while maintaining the ability to transform voltage levels across the required range for proper signal interpretation in internal circuits.
Data Source
AI summary
A level shifter includes a voltage distributor for receiving an input signal and respectively outputting a first signal and a second signal at a first node and a second node according to the input signal; and an output circuit coupled to the voltage distributor for generating an output signal according to the first signal and the second signal, wherein the voltage distributor includes: a first transistor having a first electrode, a second electrode coupled to the first node, and a first control electrode for receiving the input signal; a switch coupled between the first node and the second node for selectively establishing an electrical connection between the first and the second nodes; and a second transistor having a third electrode coupled to the second node, a fourth electrode, and a second control electrode coupled to the first node.