Voltage Divider Bias Timing for Fast Multi-Level Output
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Solution Overview
Problem
Voltage dividers often exhibit slow stabilization times and require multiple units to achieve multiple voltage levels, which can lead to space and area penalties in memory cell arrays.
Innovation Solution
A control circuit that biases a voltage divider's pull up unit using an analog signal and incorporates a delay unit to control the timing of the pull up unit's activation relative to the pull down unit, allowing for multiple voltage levels without the need for multiple voltage dividers or large areas, by delaying the activation of the pull up unit during a delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a voltage divider is used to produce output voltage, then voltage division function is achieved, but stabilization time is slow
Solution Approach 1:
The patent applies preliminary action by pre-charging the output node through the pull-up unit before the voltage divider operation. The pull-up unit is activated in advance to charge the output node capacitance, so when the voltage divider switches occur, the output node is already prepared with charge, significantly reducing stabilization time while maintaining voltage stability.
2Adaptability or versatility
If multiple voltage dividers are used to achieve multiple voltage levels, then voltage level diversity is improved, but area and space requirements increase
Solution Approach 1:
The patent implements universality by designing a single voltage divider circuit that can generate multiple voltage levels (Vppu1, Vppu2, etc.) through a shared pull-up unit controlled by different gate voltages. Instead of requiring separate voltage dividers for each voltage level, one multi-functional voltage divider serves all voltage level needs, dramatically reducing circuit area while maintaining full voltage level diversity.
Solution Approach 2:
The patent applies parameter changes by varying the gate voltage of the pull-up unit to generate different output voltage levels. By changing the control parameter (gate voltage) rather than changing the physical circuit structure, the same voltage divider can produce multiple voltage levels dynamically, avoiding the need for multiple parallel voltage divider circuits.
3Ease of operation
If pull up unit is activated simultaneously with pull down unit, then circuit operation is simplified, but stabilization time increases
Solution Approach 1:
The patent applies preliminary action by activating the pull-up unit before the pull-down unit. The pull-up unit prepares the output node by charging it in advance, so when the pull-down unit activates, the voltage transition occurs more quickly with less settling time required, reducing overall stabilization time while maintaining operational simplicity through controlled sequencing.
Data Source
AI summary
One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.